---
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky
-- 12/31/98
-- Version 1.2
-- Notes: This file implements the Digital Camera, a.k.a., DIG_CAM, device.
--	  So far, DIG_CAM consists of a memory module, bios module, and...
--

--*************************************************************************--

library lsi_10k;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use lsi_10k.all;

--*************************************************************************--

entity DIG_CAM is
	generic( COMPRESSION : INTEGER range 1 to 4 := 4);
	port(	scan_clk : in STD_LOGIC;
		scan_data : in UNSIGNED(7 downto 0);
		clk : in STD_LOGIC;
		rst : in STD_LOGIC;
		start_capture: out STD_LOGIC;
		rd_out : out STD_LOGIC;
		wr_out : out STD_LOGIC;
		ior_out : out STD_LOGIC;
		iow_out : out STD_LOGIC;
		data_out: out UNSIGNED(31 downto 0);
		addr_out: out UNSIGNED(22 downto 0) );
end DIG_CAM;

--*************************************************************************--

architecture BHV_DIG_CAM of DIG_CAM is

	--
	-- component declarations
	--
	component MIPS
		port( clk : in STD_LOGIC;
		      rst : in STD_LOGIC;
	              cs  : in STD_LOGIC;
		      data : inout UNSIGNED(31 downto 0);
	              addr : out UNSIGNED(22 downto 0);
	              rd   : out STD_LOGIC;
	              wr   : out STD_LOGIC;
		      rdy  : in STD_LOGIC;
		      hrq : in STD_LOGIC;
		      hlda : out STD_LOGIC );
	end component;

	component BIOS
	    	generic( COMP_RATIO : INTEGER := 4 );	
		port( clk  : in STD_LOGIC;
		      rst  : in STD_LOGIC;
		      data : out UNSIGNED(31 downto 0); 
		      addr : out UNSIGNED(22 downto 0);
		      rd   : out STD_LOGIC;
		      wr   : out STD_LOGIC;
		      rdy  : in STD_LOGIC;
		      cs   : out STD_LOGIC );
	end component;

	component MEMORY
		generic( MAX_MEM_SIZE : INTEGER := 350 );
		port( clk  : in STD_LOGIC;
		      rst  : STD_LOGIC;
     		      data : inout UNSIGNED(31 downto 0); 
		      addr : in UNSIGNED(22 downto 0);
		      rd   : in STD_LOGIC;
	              wr   : in STD_LOGIC);
	end component;


	component BRIDGE
		generic(START_ADDR : INTEGER := 512);
		port(	rst  : in STD_LOGIC;
			clk  : in STD_LOGIC;
			data : inout UNSIGNED(31 downto 0);
			addr : in UNSIGNED(22 downto 0);
			rd   : in STD_LOGIC;
			wr   : in STD_LOGIC;
			rdy  : out STD_LOGIC;
			pdata   : inout UNSIGNED(31 downto 0);
			paddr   : out UNSIGNED(22 downto 0);
			ior     : out STD_LOGIC;
			iow     : out STD_LOGIC;
			ale     : out STD_LOGIC;
			iochrdy : in STD_LOGIC);
	end component;

	component CODEC
		generic( IN_REG_ADDR : INTEGER:=1024;
			 OUT_REG_ADDR : INTEGER:=1025;
			 STAT_REG_ADDR : INTEGER:=1026;
			 CONT_REG_ADDR : INTEGER:=1027;
			 COMPRESSION : INTEGER:=4);
		port( clk  : in STD_LOGIC;
		      rst  : in STD_LOGIC;
		      pdata : inout UNSIGNED(31 downto 0); 
		      paddr : in UNSIGNED(22 downto 0);
		      ior   : in STD_LOGIC;
	              iow   : in STD_LOGIC;
		      ale   : in STD_LOGIC;
		      iochrdy : out STD_LOGIC );
	end component;

	component CCD 
	generic( IMAGE_READY_REG : INTEGER := 512;
		 IMAGE_START_REG : INTEGER := 513;
                 DATA_REG : INTEGER := 514;
		 IMAGE_WIDTH : INTEGER range 1 to 1024 := 16;  
	         IMAGE_HEIGHT : INTEGER range 1 to 1024 := 16);
	port( scan_clk : in STD_LOGIC;
              scan_data : in UNSIGNED(7 downto 0);
	      clk  : in STD_LOGIC;
	      rst  : in STD_LOGIC;
	      start_capture: out STD_LOGIC;
	      pdata : inout UNSIGNED(31 downto 0); 
	      paddr : in UNSIGNED(22 downto 0);
	      ior   : in STD_LOGIC;
              iow   : in STD_LOGIC;
	      ale   : in STD_LOGIC;
	      iochrdy : out STD_LOGIC;      
	      dior : in STD_LOGIC;
	      dreq : out STD_LOGIC;
	      dack : in STD_LOGIC;
	      ddata : out UNSIGNED(31 downto 0));
	end component;

	component PPP
		generic( A_PORT_ADDR : INTEGER:=1028;
			 B_PORT_ADDR : INTEGER:=1029;
			 C_PORT_ADDR : INTEGER:=1030;
			 CONT_REG_ADDR : INTEGER:=1031);
		port( clk  : in STD_LOGIC;
		      rst  : in STD_LOGIC;
		      pdata : inout UNSIGNED(31 downto 0); 
		      paddr : in UNSIGNED(22 downto 0);
		      ior   : in STD_LOGIC;
	              iow   : in STD_LOGIC;
		      ale   : in STD_LOGIC;
		      iochrdy : out STD_LOGIC;
		      paen : out STD_LOGIC;
		      pben : out STD_LOGIC;
		      pcen : out UNSIGNED(7 downto 0);
		      pai  : in UNSIGNED(7 downto 0);
		      pbi  : in UNSIGNED(7 downto 0);
		      pci  : in UNSIGNED(7 downto 0);
	 	      pao  : out UNSIGNED(7 downto 0);
		      pbo  : out UNSIGNED(7 downto 0);
		      pco  : out UNSIGNED(7 downto 0));
	end component;

	component PC16550
		generic(INPUT_ADDR : INTEGER := 3000);
		port(clk  : in STD_LOGIC;
		     rst  : in STD_LOGIC;
		     pdata : inout UNSIGNED (31 downto 0); 
		     paddr : in UNSIGNED (22 downto 0);
		     ior   : in STD_LOGIC;
		     iow   : in STD_LOGIC;
		     ale   : in STD_LOGIC;
		     iochrdy : out STD_LOGIC;
		     sout    : out STD_LOGIC );
	end component;

	component DMA
		generic(COMMAND_ADDR : INTEGER := 400;
			MODE_ADDR : INTEGER := 401;
			BASE_WORD_ADDR : INTEGER := 402;
			BASE_ADDR_ADDR : INTEGER := 403);
		port( clk  : in STD_LOGIC;
		      rst  : in STD_LOGIC;
		      data : in UNSIGNED(31 downto 0); 
		      addr : inout UNSIGNED(22 downto 0);
		      rd   : inout STD_LOGIC;
	              wr   : inout STD_LOGIC;
		      dreq : in STD_LOGIC;
		      dack : out STD_LOGIC;
		      hrq  : out STD_LOGIC;
		      hlda : in STD_LOGIC;
		      ior  : out STD_LOGIC );
	end component;

	--
	-- define signals for the bus
	--
	signal data : UNSIGNED(31 downto 0);
	signal addr : UNSIGNED(22 downto 0);
	signal rd, wr, rdy : STD_LOGIC;
	signal bios_done : STD_LOGIC;
	signal hrq, hlda : STD_LOGIC;
	signal pdata : UNSIGNED(31 downto 0);
	signal paddr : UNSIGNED(22 downto 0);
	signal ior, iow, ale, iochrdy : STD_LOGIC;
	signal sout : STD_LOGIC;
	signal paen, pben : STD_LOGIC;
	signal pcen, pao, pbo, pco, pai, pbi, pci: UNSIGNED(7 downto 0); 
	signal dreq, dack, dior : STD_LOGIC;
begin
	data_out <= data;
	addr_out <= addr;
	rd_out <= rd;
	wr_out <= wr;
	ior_out <= ior;
	iow_out <= iow;

	--
	-- instantiate the BIOS and MEMORY devices
	--
	MIPS_1: MIPS port map(clk, rst, bios_done, data, addr, rd, wr, rdy, 
			      hrq, hlda);
	BIOS_1: BIOS generic map (COMPRESSION)
	    port map(clk, rst, data, addr, rd, wr, rdy, bios_done);

	MEMORY_1: MEMORY port map(clk, rst, data, addr, rd, wr);
	BRIDGE_1: BRIDGE port map(rst, clk, data, addr, rd, wr, rdy, 
				  pdata, paddr, ior, iow, ale, iochrdy); 
	CODEC_1: CODEC generic map(COMPRESSION => COMPRESSION)
	    port map(clk, rst, pdata, paddr, ior, iow, ale, 
		     iochrdy);
	CCD_1: CCD port map(	scan_clk, scan_data, clk, rst,
				start_capture, pdata, paddr, 
				ior, iow, ale, iochrdy, dior, dreq, 
				dack, data);
	PC16550_1: PC16550
	    port map(clk, rst, pdata, paddr, ior, iow, ale, 
		     iochrdy, sout);
	PPP_1: PPP
	    port map(clk, rst, pdata, paddr,ior, iow, ale, 
			    iochrdy, paen, pben, pcen, pai, pbi, pci,
			    pao, pbo, pco);
	DMA_1: DMA port map(clk, rst, data, addr, rd, wr, dreq, dack,
			    hrq, hlda, dior);

end BHV_DIG_CAM;
			     

--*************************************************************************--
-- end of file --