Steps for power analysis of the reference design(DIGCAM) using the provided 
synthesis scripts.

_______________________________________________________________________________

Synthesizing individual cores in DIGCAM.

1. For each core there exists a file called CORE_syn.scr.  Running this script
by itself will synthesize the given core and produce two file:

	- CORE_GATE.db (Synopsys internal format)
	- CORE_GATE.vhd (VHDL gate-level file)

To run the script, enter the follwoing command in dc_shell

	include CORE_syn.scr (Please note that this script will exit 
			      dc_shell upon exit.  Remove "exit" from
			      the script file to avoid this)

_______________________________________________________________________________

MODIFICATIONS: The following two modificattion to the gate-level vhdl files in
order for simulation to work.

1. Comment out the line that define UNSIGNED type.  This is not needed and will
result in errors.

2. Add the following configuration to the end of the file.

configuration CFG_CORE_SYN of CORE is
	for SYN
	end for;
end CFG_CORE_SYN;

_______________________________________________________________________________

Synthesizing and simulating the DIG_CAM.

1. Synthesize the entire design using the DIG_CAM_syn.scr.

2. Modify the gate-level VHDL output as described above.

3. Change the DIG_CAM_TB.vhd.  In the configuration for the DIG_CAM_TB, ensure 
that it is using the synthesized gate-level design. 

	ie. for DIG_CAM_1 : DIG_CAM use configuration WORK.CFG_DIG_CAM_SYN;
	    end for;

4. Run the simulation by running sim.scr from the command prompt.  This will
output a toggle file "dig_cam_vss_toggle_count".

5. Convert the toggle file using the following command.

	sim2dp -vss dig_cam_vss_toggle_count > dig_cam_sa.scr

	NOTE: sim2dp is a script provided within the synopsys package.

6. Then run the "power.scr" or "power_high.scr" file from within dc_shell to
provide the power analysis results.