Reference designs

A reference design is a pre-designed architecture, consisting of processor cores, memories, buses, and numerous peripheral cores, that can be used as the starting point for a design. As mentioned in the overview of the Dalton project, we are mainly interested in parameterized reference designs, and more specifically, the exploration of power, performance and size for various parameter settings. We have developed some simple reference designs for experimentation purposes. They are written in Synopsys synthesizable VHDL and we make them available here for use by others. We would appreciate hearing from you if you find them useful.

Our Reference Design(DIGCAM):

  • Version 1.4 Schematic and Source Code
  • Version 1.3 Schematic and Source Code
  • Version 1.2 Schematic and Source Code
  • Parameterization statistics

    • Dalton project publications

    Please see the Dalton publications page.

    Papers by others related to reference designs

  • Single-chip reference designs
  • Heterogeneous Reconfigurable Systems , Rabaey et al, IEEE Workshop on Signal Processing Systems, 1997. Describes the Pleiades "heterogeneous reconfigurable architecture" being developed at UC Berkeley, consisting of several arithmetic processors, a communication network, a control processor, a configurable datapath, and configurable logic.
  • Experiences with System Level Design for Consumer ICs, van Meerbergen et al, IEEE CS Workshop on VLSI, 1998.
    Describes the need for "silicon platforms" and gives details of a particular example, a multiwindow TV, from which ideas for a general platform may be gleaned.
  • An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology, van der Wolf et al, Int. Workshop on Hardware/Software Codesign, 1999.
    Describes the need for a methodology in which an architecture is designed and modeled, and then tools are used to assist in evaluating different mappings of an applications to that architecture.
  • Integrating processors and programmable logic
  • Berkeley's Brass Project has a nice summary of approaches.
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  • Simulation/emulation for systems-on-a-chip
  • Functional Verification of Large ASICs Evans et al, DAC, 1998. Lots of excellent data on the various tasks required to build on 3 large ASICs built by Nortel. Concludes that functional verification was the dominant task, and that extensive emulation was crucial in finding bugs.
  • Digital System Simulation: Methodologies and Examples Olukotun et al, DAC, 1998. Describes different levels of simulation for large ASICs.

    • Related projects/products

  • National Semiconductor's Adaptive Systems-On-A-Chip
  • Berkeley Reconfigurable Architectures, Systems and Software
  • Velocity by VLSI Technology -- A commercial reference design
    EE Times article on Velocity
  • Aptix Reconfigurable System Prototyping (board level)

    • Other related information

  • Seminconductor Industry Association Roadmap 1997 Summary
  • Full Roadmap 1999

    • Return to Dalton home page

    December 9, 1998