Keywords:
reg
default
value:
x
default
size:
1 bit
The fundamental difference between nets and registers is that registers have to be assigned values explicitly. That value is held until a new assignment is made. This property can, for example, be used to model a E-type flip flop as shown in figure below, with corresponding Verilog code given below.
module E_ff(q, data, enable, reset, clock); output q; input data, enable, reset, clock; reg q; always @(posedge clock) // whenever the clock makes a transition to 1 if (reset == 0) q = 1'b0; else if (enable==1) q = data; // implicitly : else q = q: endmodule
As a contrast, if we go into a higher level module, for example the stimulus shown below, the output from the E_ff would have to be assigned as a net so that the E_ff module can drive its value. So now q is a wire.
module stimulus; reg data, enable, clock, reset; wire q; initial begin clock = 1'b0; forever #5 clock = ~clock; end E_ff eff0(q, data, enable, reset, clock); // as with 'c' in the previous section, the wire 'q' will now have its // value driven into it by the E_ff module. initial begin reset = 1'b0; #10 reset = 1'b1; data = 1'b1; #20 enable = 1; #10 data = 1'b0; #10 data = 1'b1; #10 enable = 0; #10 data = 1'b0; #10 data = 1'b1; #10 enable = 1; #10 reset = 1'b0; #30 $finish; end initial $monitor($time, " q = %d", q); endmodule