LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY select_and_add_tester IS
END select_and_add_tester;
--
ARCHITECTURE testing OF select_and_add_tester IS
  COMPONENT select_and_add
    PORT (a, b, c : IN std_logic_vector(7 DOWNTO 0);
          sa, sb, sc : IN std_logic; 
          z : INOUT std_logic_vector(7 DOWNTO 0));
  END COMPONENT;
  FOR original : select_and_add USE 
      ENTITY WORK.select_and_add(bussing);
  FOR synthesized : select_and_add USE 
      ENTITY WORK.LOGIC8(exemplar)
      PORT MAP (
                a(7), a(6), a(5), a(4), a(3), a(2), a(1), a(0),
                b(7), b(6), b(5), b(4), b(3), b(2), b(1), b(0),
                c(7), c(6), c(5), c(4), c(3), c(2), c(1), c(0),
                d(7), d(6), d(5), d(4), d(3), d(2), d(1), d(0),
                s,
                z(7), z(6), z(5), z(4), z(3), z(2), z(1), z(0)
                );
  SIGNAL a, b, c, d : std_logic_vector(7 DOWNTO 0);
  SIGNAL sa, ab, sc : std_logic;
  SIGNAL z_o, z_s : std_logic_vector(7 DOWNTO 0);
BEGIN
  s <= '0', '1' AFTER 35 US, '0' AFTER 50 US;
  a <= "01010110", "11101100" AFTER 20 US, "00011010" AFTER 30 US, 
       "01010010" AFTER 40 US, "01111110" AFTER 50 US,
       "10000010" AFTER 60 US, "00010000" AFTER 70 US;
  b <= "01110110", "11110100" AFTER 20 US, "01011010" AFTER 30 US, 
       "01010010" AFTER 50 US, "01111110" AFTER 60 US,
       "11111000" AFTER 70 US, "01010101" AFTER 80 US;
  c <= "01110110", "11111100" AFTER 10 US, "00111010" AFTER 20 US, 
       "01111010" AFTER 30 US, "01000010" AFTER 40 US,
       "11010010" AFTER 50 US, "01010000" AFTER 60 US;
  d <= "11000110", "00111100" AFTER 20 US, "00011110" AFTER 30 US, 
       "01111110" AFTER 35 US, "01100010" AFTER 75 US;
  original: select_and_add PORT MAP (a, b, c, d, s, z_o);
  synthesized: select_and_add PORT MAP (a, b, c, d, s, z_s);
END testing;