LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY priority_encoder_tester IS
END priority_encoder_tester;
--
ARCHITECTURE testing OF priority_encoder_tester IS
  COMPONENT priority_encoder
    PORT (a : IN std_logic_vector(7 DOWNTO 0);
          n : OUT std_logic_vector(2 DOWNTO 0); 
          z : INOUT std_logic_vector(7 DOWNTO 0);
          f : OUT std_logic );
  END COMPONENT;
  FOR original : priority_encoder USE 
      ENTITY WORK.priority_encoder(behavioral);
  FOR synthesized : priority_encoder USE 
      ENTITY WORK.LOGIC7(exemplar)
      PORT MAP (a(7), a(6), a(5), a(4), a(3), a(2), a(1), a(0),
                n(2), n(1), n(0),
                z(7), z(6), z(5), z(4), z(3), z(2), z(1), z(0),
                f );
  SIGNAL a : std_logic_vector(7 DOWNTO 0);
  SIGNAL n_o, n_s : std_logic_vector(2 DOWNTO 0);
  SIGNAL z_o, z_s : std_logic_vector(7 DOWNTO 0);
  SIGNAL f_o, f_s : std_logic;
BEGIN
  a <= "01010110", "11101100" AFTER 20 US, "00011010" AFTER 30 US, 
       "01010010" AFTER 40 US, "01111110" AFTER 50 US,
       "10000010" AFTER 60 US, "00010000" AFTER 70 US,
       "00000000" AFTER 80 US, "01000110" AFTER 85 US, 
       "10100000" AFTER 90 US, "00000000" AFTER 95 US,
       "11111111" AFTER 99 US;
  original: priority_encoder PORT MAP (a, n_o, z_o, f_o);
  synthesized: priority_encoder PORT MAP (a, n_s, z_s, f_s);
END testing;