LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY divider_counter_tester IS
END divider_counter_tester;
--
ARCHITECTURE testing OF divider_counter_tester IS
  COMPONENT divider_counter
    PORT (clock, reset : IN std_logic; divide_out : OUT std_logic);
  END COMPONENT;
  FOR original : divider_counter USE 
      ENTITY WORK.divider_counter(behavioral);
  FOR synthesized : divider_counter USE 
      ENTITY WORK.COUNT6(exemplar)
      PORT MAP (clock, reset, divide_out);
  SIGNAL clock, reset : std_ulogic := '0';
  SIGNAL divide_out_o, divide_out_s : std_logic;
BEGIN
  reset <= '1', '0' AFTER 2.5 US, '1' AFTER 9.5 US, '0' AFTER 12.5 US;
  clock <= NOT clock AFTER 1 US WHEN NOW <= 200 US ELSE '0';
  original: divider_counter PORT MAP (clock, reset, divide_out_o);
  synthesized: divider_counter PORT MAP (clock, reset, divide_out_s);
END testing;