LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY simple_alu_tester IS
END simple_alu_tester;
--
ARCHITECTURE testing OF simple_alu_tester IS
  COMPONENT simple_alu
    PORT (a, b : IN std_logic_vector(3 DOWNTO 0);
          code_in : IN std_logic_vector(2 DOWNTO 0); 
          flags : INOUT std_logic_vector(2 DOWNTO 0);
          z_out : OUT std_logic_vector(3 DOWNTO 0));
  END COMPONENT;
  FOR original : simple_alu USE 
      ENTITY WORK.simple_alu(behavioral);
  FOR synthesized : simple_alu USE 
      ENTITY WORK.LOGIC5(exemplar)
      PORT MAP (a(3), a(2), a(1), a(0),
                b(3), b(2), b(1), b(0),
                code_in(2), code_in(1), code_in(0),
                flags(2), flags(1), flags(0),
                z_out(3), z_out(2), z_out(1), z_out(0) );
  SIGNAL a, b : std_logic_vector(3 DOWNTO 0);
  SIGNAL code_in : std_logic_vector(2 DOWNTO 0);
  SIGNAL flags_o, flags_s : std_logic_vector(2 DOWNTO 0);
  SIGNAL z_out_o, z_out_s : std_logic_vector(3 DOWNTO 0);
BEGIN
  a <= "0000", "1011" AFTER 20 US, "0110" AFTER 30 US, 
       "0010" AFTER 40 US, "0110" AFTER 50 US,
       "1010" AFTER 60 US, "0001" AFTER 70 US;
  b <= "0000", "0010" AFTER 20 US, "0110" AFTER 30 US, 
       "1010" AFTER 40 US, "0001" AFTER 50 US,
       "0010" AFTER 60 US, "0110" AFTER 70 US;
  code_in <= "010", "100" AFTER 20 US, "010" AFTER 35 US, 
             "110" AFTER 45 US, "111" AFTER 55 US, "001" AFTER 60 US,
             "011" AFTER 65 US, "101" AFTER 70 US, "000" AFTER 75 US;
  original: simple_alu PORT MAP (a, b, code_in, flags_o, z_out_o);
  synthesized: simple_alu PORT MAP (a, b, code_in, flags_s, z_out_s);
END testing;