LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY walking1_counter_tester IS
END walking1_counter_tester;
--
ARCHITECTURE testing OF walking1_counter_tester IS
  COMPONENT walking1_counter
    PORT (clock, reset : IN std_logic;
        count_out : INOUT std_logic_vector (7 DOWNTO 0));
  END COMPONENT;
  FOR original : walking1_counter USE 
      ENTITY WORK.walking1_counter(dataflow);
  FOR synthesized : walking1_counter USE 
      ENTITY WORK.COUNT5(exemplar)
      PORT MAP (clock, reset, 
                count_out(7), count_out(6), count_out(5),
                count_out(4), count_out(3), count_out(2),
                count_out(1), count_out(0) );
  SIGNAL clock, reset : std_ulogic := '0';
  SIGNAL count_out_o, count_out_s : std_logic_vector (7 DOWNTO 0);
BEGIN
  reset <= '1', '0' AFTER 2.5 US, '1' AFTER 9.5 US, '0' AFTER 12.5 US;
  clock <= NOT clock AFTER 1 US WHEN NOW <= 200 US ELSE '0';
  original: walking1_counter PORT MAP (clock, reset, count_out_o);
  synthesized: walking1_counter PORT MAP (clock, reset, count_out_s) ;
END testing;