LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY basic_detector_tester IS
END basic_detector_tester;
--
ARCHITECTURE testing OF basic_detector_tester IS
  COMPONENT basic_detector
    PORT (x, clk : IN std_logic; z : INOUT std_logic);
  END COMPONENT;
  FOR original : basic_detector USE 
      ENTITY WORK.basic_detector(behavioral);
  FOR synthesized : basic_detector USE 
      ENTITY WORK.REG4(exemplar)
      PORT MAP (x, clk, z);
  SIGNAL x, clk : std_logic := '0';
  SIGNAL z_o, z_s : std_logic;
BEGIN
  clk <= NOT clk AFTER 3 US WHEN NOW <= 50 US; ELSE clk;
  x <= NOT x AFTER 5 US WHEN NOW <= 50 US; ELSE x;
  original: basic_detector PORT MAP (x, clk, z_o);
  synthesized: basic_detector PORT MAP (x, clk, z_s);
END testing;