LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY loadable_random_counter_tester IS
END loadable_random_counter_tester;
--
ARCHITECTURE testing OF loadable_random_counter_tester IS
  COMPONENT loadable_random_counter
    PORT (clock, preset, clear, preload : IN std_logic;
          count_in : IN std_logic_vector (3 DOWNTO 0);
          count_out : INOUT std_logic_vector (3 DOWNTO 0));
  END COMPONENT;
  FOR original : loadable_random_counter USE 
      ENTITY WORK.loadable_random_counter(behavioral);
  FOR synthesized : loadable_random_counter USE 
      ENTITY WORK.COUNT4(exemplar)
      PORT MAP (clock, preset, clear, preload, 
                count_in(3), count_in(2), count_in(1), count_in(0), 
                count_out(3), count_out(2), count_out(1), count_out(0) );
  SIGNAL clock, preset, clear, preload : std_ulogic := '0';
  SIGNAL count_in : std_logic_vector (3 DOWNTO 0);
  SIGNAL count_out_o, count_out_s : std_logic_vector (3 DOWNTO 0);
BEGIN
  clear <= '1', '0' AFTER 3.5 US, '1' AFTER 25.5 US, '0' AFTER 31.5 US,
           '1' AFTER 42.5 US, '0' AFTER 48.5 US;
  clock <= NOT clock AFTER 1 US WHEN NOW <= 200 US ELSE '0';
  preset <= '0', '1' AFTER 35.5 US, '0' AFTER 43.5 US, '1' AFTER 45.5 US,
            '0' AFTER 47.5 US;
  preload <= '0', '1' AFTER 9.5 US, '0' AFTER 11.5 US, '1' AFTER 40.5 US,
             '0' AFTER 50.5 US;
  count_in <= "1101", "1001" AFTER 20.5 US; 
  original: loadable_random_counter 
          PORT MAP (clock, preset, clear, preload, count_in, count_out_o);
  synthesized: loadable_random_counter 
          PORT MAP (clock, preset, clear, preload, count_in, count_out_s) ;
END testing;