LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY internal_flag_tester IS
END internal_flag_tester;
--
ARCHITECTURE testing OF internal_flag_tester IS
  COMPONENT internal_flag
    PORT (d, c, a : IN std_logic; z : INOUT std_logic);
  END COMPONENT;
  FOR original : internal_flag USE 
      ENTITY WORK.internal_flag(behavioral);
  FOR synthesized : internal_flag USE 
      ENTITY WORK.REG3(exemplar)
      PORT MAP (d, c, a, z);
  SIGNAL d, c, a : std_logic;
  SIGNAL z_o, z_s : std_logic;
BEGIN
  a <= '0', '1' AFTER 05 US, '0' AFTER 40 US, '1' AFTER 45 US, '0' AFTER 60 US;
  c <= '0', '1' AFTER 25 US, '0' AFTER 30 US, '1' AFTER 40 US, '0' AFTER 45 US;
  d <= '0', '1' AFTER 20 US, '0' AFTER 35 US, '1' AFTER 50 US, '0' AFTER 55 US;
  original: internal_flag PORT MAP (d, c, a, z_o);
  synthesized: internal_flag PORT MAP (d, c, a, z_s);
END testing;