LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY seven_segment_decoder_tester IS
END seven_segment_decoder_tester;
--
ARCHITECTURE testing OF seven_segment_decoder_tester IS
  COMPONENT seven_segment_decoder
    PORT (bcd_in : IN std_logic_vector(3 DOWNTO 0); 
          ssd_out : OUT std_logic_vector(6 DOWNTO 0));
  END COMPONENT;
  FOR original : seven_segment_decoder USE 
      ENTITY WORK.seven_segment_decoder(dataflow);
  FOR synthesized : seven_segment_decoder USE 
      ENTITY WORK.LOGIC3(exemplar)
      PORT MAP (bcd_in(3), bcd_in(2), bcd_in(1), bcd_in(0),
                ssd_out(6), ssd_out(5), ssd_out(4), ssd_out(3), 
                ssd_out(2), ssd_out(1), ssd_out(0) );
  SIGNAL bcd_in : std_logic_vector(3 DOWNTO 0);
  SIGNAL ssd_out_o, ssd_out_s : std_logic_vector(6 DOWNTO 0);
BEGIN
  bcd_in <= "0000", "1011" AFTER 20 US, "0110" AFTER 30 US, 
            "0010" AFTER 40 US, "0110" AFTER 50 US, 
            "0010" AFTER 60 US, "0110" AFTER 70 US, 
            "1010" AFTER 80 US, "1110" AFTER 90 US;
  original: seven_segment_decoder PORT MAP (bcd_in, ssd_out_o);
  synthesized: seven_segment_decoder PORT MAP (bcd_in, ssd_out_s);
END testing;