LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY universal_synchronous_counter_tester IS
END universal_synchronous_counter_tester;
--
ARCHITECTURE testing OF universal_synchronous_counter_tester IS
  COMPONENT universal_synchronous_counter
    PORT (clock, reset, enable, updown : IN std_logic;
        count_out : INOUT std_logic_vector (7 DOWNTO 0));
  END COMPONENT;
  FOR original : universal_synchronous_counter USE 
      ENTITY WORK.universal_synchronous_counter(behavioral);
  FOR synthesized : universal_synchronous_counter USE 
      ENTITY WORK.COUNT3(exemplar)
      PORT MAP (clock, reset, enable, updown, 
                count_out(7), count_out(6), count_out(5),
                count_out(4), count_out(3), count_out(2),
                count_out(1), count_out(0) );
  SIGNAL clock, reset, enable, updown : std_ulogic := '0';
  SIGNAL count_out_o, count_out_s : std_logic_vector (7 DOWNTO 0);
BEGIN
  reset <= '1', '0' AFTER 2.5 US, '1' AFTER 15.5 US, '0' AFTER 17.5 US;
  clock <= NOT clock AFTER 1 US WHEN NOW <= 200 US ELSE '0';
  enable <= '1', '0' AFTER 30.5 US, '1' AFTER 50.5 US;
  updown <= '1', '0' AFTER 90.5 US;
  original: universal_synchronous_counter 
          PORT MAP (clock, reset, enable, updown, count_out_o);
  synthesized: universal_synchronous_counter 
          PORT MAP (clock, reset, enable, updown, count_out_s) ;
END testing;