LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY basic_d_flop_tester IS
END basic_d_flop_tester;
--
ARCHITECTURE testing OF basic_d_flop_tester IS
  COMPONENT basic_d_flop
    PORT (d, c : IN std_logic; z : INOUT std_logic);
  END COMPONENT;
  FOR original : basic_d_flop USE 
      ENTITY WORK.basic_d_flop(behavioral);
  FOR synthesized : basic_d_flop USE 
      ENTITY WORK.REG2(exemplar)
      PORT MAP (d, c, z);
  SIGNAL d, c : std_logic;
  SIGNAL z_o, z_s : std_logic;
BEGIN
  c <= '0', '1' AFTER 25 US, '0' AFTER 30 US, '1' AFTER 40 US, '0' AFTER 45 US;
  d <= '0', '1' AFTER 20 US, '0' AFTER 35 US, '1' AFTER 50 US, '0' AFTER 55 US;
  original: basic_d_flop PORT MAP (d, c, z_o);
  synthesized: basic_d_flop PORT MAP (d, c, z_s);
END testing;