LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY cascadable_comparator_tester IS
END cascadable_comparator_tester;
--
ARCHITECTURE testing OF cascadable_comparator_tester IS
  COMPONENT cascadable_comparator
    PORT (a, b : IN std_logic_vector(3 DOWNTO 0);
          comp_in : IN std_logic_vector(2 DOWNTO 0); 
          comp_out : OUT std_logic_vector(2 DOWNTO 0));
  END COMPONENT;
  FOR original : cascadable_comparator USE 
      ENTITY WORK.cascadable_comparator(dataflow);
  FOR synthesized : cascadable_comparator USE 
      ENTITY WORK.LOGIC2(exemplar)
      PORT MAP (a(3), a(2), a(1), a(0),
                b(3), b(2), b(1), b(0),
                comp_in(2), comp_in(1), comp_in(0),
                comp_out(2), comp_out(1), comp_out(0) );
  SIGNAL a, b : std_logic_vector(3 DOWNTO 0);
  SIGNAL comp_in : std_logic_vector(2 DOWNTO 0);
  SIGNAL comp_out_o, comp_out_s : std_logic_vector(2 DOWNTO 0);
BEGIN
  a <= "0000", "1011" AFTER 20 US, "0110" AFTER 30 US, 
       "0010" AFTER 40 US, "0110" AFTER 50 US;
  b <= "0000", "0010" AFTER 20 US, "0110" AFTER 30 US, 
       "1010" AFTER 40 US, "0001" AFTER 50 US;
  comp_in <= "010", "100" AFTER 20 US, "010" AFTER 35 US, "110" AFTER 45 US;
  original: cascadable_comparator PORT MAP (a, b, comp_in, comp_out_o);
  synthesized: cascadable_comparator PORT MAP (a, b, comp_in, comp_out_s);
END testing;