LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY asynch_reset_detector_tester IS
END asynch_reset_detector_tester;
--
ARCHITECTURE testing OF asynch_reset_detector_tester IS
  COMPONENT asynch_reset_detector
    PORT (x, r, clk : IN std_logic; z : INOUT std_logic);
  END COMPONENT;
  FOR original : asynch_reset_detector USE 
      ENTITY WORK.asynch_reset_detector(behavioral);
  FOR synthesized : asynch_reset_detector USE 
      ENTITY WORK.machine1(exemplar)
      PORT MAP (x, r, clk, z);
  SIGNAL x, r, clk : std_logic := '0';
  SIGNAL z_o, z_s : std_logic;
BEGIN
  clk <= NOT clk AFTER 3.01 US WHEN NOW <= 50 US ELSE clk;
  x <= NOT x AFTER 5 US WHEN NOW <= 50 US ELSE x;
  r <= '0', '1' AFTER 40 US, '0' AFTER 43 US;
  original: asynch_reset_detector PORT MAP (x, r, clk, z_o);
  synthesized: asynch_reset_detector PORT MAP (x, r, clk, z_s);
END testing;