LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY incomplete_if_tester IS
END incomplete_if_tester;
--
ARCHITECTURE testing OF incomplete_if_tester IS
  COMPONENT incomplete_if
    PORT (a, b : IN std_logic; x, z : OUT std_logic);
  END COMPONENT;
  FOR original : incomplete_if USE 
      ENTITY WORK.incomplete_if(behavioral);
  FOR synthesized : incomplete_if USE 
      ENTITY WORK.LOGIC14(exemplar)
      PORT MAP (a, b, x, z);
  SIGNAL a, b : std_logic;
  SIGNAL z_o, z_s, x_o, x_s : std_logic;
BEGIN
  a <= '0', '1' AFTER 25 US, '0' AFTER 35 US, '1' AFTER 45 US;
  b <= '0', '1' AFTER 20 US, '1' AFTER 30 US, '1' AFTER 40 US;
  original: incomplete_if PORT MAP (a, b, x_o, z_o);
  synthesized: incomplete_if PORT MAP (a, b, x_s, z_s);
END testing;