LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY sequential_and_or_tester IS
END sequential_and_or_tester;
--
ARCHITECTURE testing OF sequential_and_or_tester IS
  COMPONENT sequential_and_or
    PORT (a, b, c : IN std_logic; z : OUT std_logic);
  END COMPONENT;
  FOR original : sequential_and_or USE 
      ENTITY WORK.sequential_and_or(behavioral);
  FOR synthesized : sequential_and_or USE 
      ENTITY WORK.LOGIC13(exemplar)
      PORT MAP (a, b, c, z);
  SIGNAL a, b, c : std_logic;
  SIGNAL z_o, z_s : std_logic;
BEGIN
  a <= '0', '1' AFTER 25 US, '0' AFTER 35 US, '1' AFTER 45 US;
  b <= '0', '1' AFTER 20 US, '1' AFTER 30 US, '1' AFTER 40 US;
  c <= '1', '0' AFTER 28 US, '1' AFTER 38 US, '0' AFTER 48 US;
  original: sequential_and_or PORT MAP (a, b, c, z_o);
  synthesized: sequential_and_or PORT MAP (a, b, c, z_s);
END testing;