LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY fault_tolerant_adder_tester IS
END fault_tolerant_adder_tester;
--
ARCHITECTURE testing OF fault_tolerant_adder_tester IS
  COMPONENT fault_tolerant_adder
    PORT (a, b : IN std_logic_vector(7 DOWNTO 0);
          s : INOUT std_logic_vector(7 DOWNTO 0); 
          failed : OUT std_logic);
  END COMPONENT;
  FOR original : fault_tolerant_adder USE 
      ENTITY WORK.fault_tolerant_adder(dataflow);
  FOR synthesized : fault_tolerant_adder USE 
      ENTITY WORK.LOGIC12(exemplar)
      PORT MAP (a(7), a(6), a(5), a(4), a(3), a(2), a(1), a(0),
                b(7), b(6), b(5), b(4), b(3), b(2), b(1), b(0),
                s(7), s(6), s(5), s(4), s(3), s(2), s(1), s(0),
                failed );
  SIGNAL a, b, s_o, s_s : std_logic_vector (7 DOWNTO 0);
  SIGNAL failed_o, failed_s : std_logic;
BEGIN
  a <= "01110000", "10110011" AFTER 20 US, "01100010" AFTER 30 US, 
       "00100010" AFTER 40 US, "01110110" AFTER 50 US;
  b <= "00110000", "01000010" AFTER 20 US, "00100110" AFTER 30 US, 
       "10001010" AFTER 40 US, "00110001" AFTER 50 US;
  original: fault_tolerant_adder PORT MAP (a, b, s_o, failed_o);
  synthesized: fault_tolerant_adder PORT MAP (a, b, s_s, failed_s);
END testing;