LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY basic_latch_tester IS
END basic_latch_tester;
--
ARCHITECTURE testing OF basic_latch_tester IS
  COMPONENT basic_latch
    PORT (s, r : IN std_logic; z : INOUT std_logic);
  END COMPONENT;
  FOR original : basic_latch USE 
      ENTITY WORK.basic_latch(behavioral);
  FOR synthesized : basic_latch USE 
      ENTITY WORK.REG0(exemplar)
      PORT MAP (s, r, z);
  SIGNAL s, r : std_logic;
  SIGNAL z_o, z_s : std_logic;
BEGIN
  s <= '0', '1' AFTER 30 US, '0' AFTER 35 US, '1' AFTER 50 US;
  r <= '0', '1' AFTER 20 US, '0' AFTER 25 US, '1' AFTER 40 US, '0' AFTER 45 US;
  original: basic_latch PORT MAP (s, r, z_o);
  synthesized: basic_latch PORT MAP (s, r, z_s);
END testing;