LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY and_or_tester IS
END and_or_tester;
--
ARCHITECTURE testing OF and_or_tester IS
  COMPONENT and_or
    PORT (a, b, c : IN std_logic_vector(3 DOWNTO 0); 
          z : OUT std_logic_vector(3 DOWNTO 0));
  END COMPONENT;
  FOR original : and_or USE 
      ENTITY WORK.and_or(dataflow);
  FOR synthesized : and_or USE 
      ENTITY WORK.LOGIC0(exemplar)
      PORT MAP (a(3), a(2), a(1), a(0),
                b(3), b(2), b(1), b(0),
                c(3), c(2), c(1), c(0),
                z(3), z(2), z(1), z(0) );
  SIGNAL a, b, c : std_logic_vector(3 DOWNTO 0);
  SIGNAL z_o, z_s : std_logic_vector(3 DOWNTO 0);
BEGIN
  a <= "0000", "1011" AFTER 20 US, "0110" AFTER 30 US, "0010" AFTER 40 US;
  b <= "0000", "0010" AFTER 20 US, "1101" AFTER 30 US, "1010" AFTER 40 US;
  c <= "0000", "0010" AFTER 20 US, "0100" AFTER 30 US, "1011" AFTER 40 US;
  original: and_or PORT MAP (a, b, c, z_o);
  synthesized: and_or PORT MAP (a, b, c, z_s);
END testing;