-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY serial_adder IS
  PORT (a, b, start, clock : IN std_logic; 
        done : OUT std_logic := '1'; 
        z : INOUT std_logic_vector (7 DOWNTO 0) := "00000000");
END serial_adder;

ARCHITECTURE behavioral OF serial_adder IS
  SIGNAL carry, busy : std_logic := '0';
  SIGNAL count : INTEGER RANGE 0 TO 7 := 0;
BEGIN
  PROCESS (clock)
    VARIABLE sum : std_logic;
  BEGIN
    sum := '0';
    IF ( clock'EVENT AND clock = '1' ) THEN
      IF start = '1' THEN done <= '0'; busy <= '1'; END IF;
      IF busy = '1' OR start = '1' THEN
        sum := a XOR b XOR carry;
        carry <= (a AND b) OR (a AND carry) OR (b AND carry);
        z <= sum & z (7 DOWNTO 1);
        IF count = 7 THEN 
          count <= 0;
          done <= '1';
          busy <= '0'; 
        ELSE
          count <= count + 1;
        END IF;
      END IF;
    END IF;
  END PROCESS;
END behavioral;