-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;


ENTITY basic_latch IS
  PORT (s, r : IN std_logic; z : OUT std_logic);
END;

ARCHITECTURE behavioral OF basic_latch IS
BEGIN
  PROCESS (s, r)
  BEGIN
    IF s = '1' THEN z <= '1';
    ELSIF r = '1' THEN z <= '0';
    END IF;
  END PROCESS;
END behavioral;