-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;


ENTITY basic_detector IS
  PORT (x, clk : IN std_logic; z : OUT std_logic);
END;

ARCHITECTURE behavioral OF basic_detector IS
  TYPE state IS (a, b, c, d);
  SIGNAL next_state, present_state : state;
BEGIN
  reg : PROCESS (clk)
  BEGIN
    IF (clk'EVENT AND clk = '1') THEN
      present_state <= next_state;
    END IF;
  END PROCESS;
  logic : PROCESS (present_state, x)
  BEGIN
    z <= '0';
    CASE present_state IS
      WHEN a =>
        IF x = '0' THEN next_state <= a;
        ELSE next_state <= b; END IF;
      WHEN b =>
        IF x = '0' THEN next_state <= c;
        ELSE next_state <= b; END IF;
      WHEN c =>
        IF x = '0' THEN next_state <= a;
        ELSE next_state <= d; END IF;
      WHEN d =>
        IF x = '0' THEN next_state <= c;
        ELSE next_state <= b; END IF;
    END CASE;
    IF present_state = d THEN z <= '1'; END IF;
  END PROCESS;
END behavioral;