-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY select_and_add IS
  PORT (a, b, c, d : IN std_logic_vector (7 DOWNTO 0); 
        s : IN std_logic;
        z : OUT std_logic_vector (7 DOWNTO 0));
END;

ARCHITECTURE bussing OF select_and_add IS
  SIGNAL ac, bd : std_logic_vector (7 DOWNTO 0);
BEGIN
  ac <= a WHEN s = '1' ELSE c;
  bd <= b WHEN s = '1' ELSE d;
  z <= ac + bd;
END bussing;