-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY priority_encoder IS
  PORT (a : IN std_logic_vector (7 DOWNTO 0); 
        n : OUT std_logic_vector (2 DOWNTO 0);
        z : OUT std_logic_vector (7 DOWNTO 0);
        f : OUT std_logic);
END;

ARCHITECTURE behavioral OF priority_encoder IS
BEGIN
  priority : PROCESS (a)
  BEGIN
    z <= "00000000"; 
    f <= '0';
    n <= "000";
    IF a(0) = '1' THEN 
      z(0) <= '1'; n <= "000"; f <= '1';
    ELSIF a(1) = '1' THEN
      z(1) <= '1'; n <= "001"; f <= '1';
    ELSIF a(2) = '1' THEN
      z(2) <= '1'; n <= "010"; f <= '1';
    ELSIF a(3) = '1' THEN
      z(3) <= '1'; n <= "011"; f <= '1';
    ELSIF a(4) = '1' THEN
      z(4) <= '1'; n <= "100"; f <= '1';
    ELSIF a(5) = '1' THEN
      z(5) <= '1'; n <= "101"; f <= '1';
    ELSIF a(6) = '1' THEN
      z(6) <= '1'; n <= "110"; f <= '1';
    ELSIF a(7) = '1' THEN
      z(7) <= '1'; n <= "111"; f <= '1';
    END IF;
  END PROCESS;
END behavioral;