-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY priority_encoder IS
  PORT (a : IN std_logic_vector (7 DOWNTO 0); 
        n : OUT std_logic_vector (2 DOWNTO 0);
        z : OUT std_logic_vector (7 DOWNTO 0);
        f : OUT std_logic);
END;

ARCHITECTURE behavioral OF priority_encoder IS
BEGIN
  priority : PROCESS (a)
    VARIABLE found : BOOLEAN;
  BEGIN
    n <= "000"; z <= "00000000"; f <= '0';
    found := FALSE;
    FOR i IN 0 TO 7 LOOP
      IF NOT found AND a(i) = '1' THEN 
        n <= int2evec(i, 3);
        z(i) <= '1';
        f <= '1';
        found := TRUE;
      END IF;
    END LOOP;
  END PROCESS;
END behavioral;

ARCHITECTURE behavioral OF priority_encoder IS
BEGIN
  priority : PROCESS (a)
  BEGIN
    n <= "000"; z <= "00000000"; f <= '0';
    FOR i IN 0 TO 7 LOOP
      IF a(i) = '1' THEN 
        n <= int2evec(i, 3);
        z(i) <= '1';
        f <= '1';
        EXIT;  -- Statement does not synthesize
      END IF;
    END LOOP;
  END PROCESS;
END behavioral;