-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY simple_alu IS
  PORT (a, b : IN std_logic_vector (3 DOWNTO 0); 
        code_in : IN std_logic_vector (2 DOWNTO 0); 
        flags : INOUT std_logic_vector (2 DOWNTO 0);
        z_out : OUT std_logic_vector (3 DOWNTO 0));
END;

ARCHITECTURE behavioral OF simple_alu IS
BEGIN
  alu : PROCESS (a, b, code_in)
    VARIABLE temp : std_logic_vector(4 DOWNTO 0);
  BEGIN
    flags <= "000";
    z_out <= "0000"; 
    CASE code_in IS
      WHEN "000" =>
        z_out <= a;
      WHEN "001" =>
        z_out <= b;
      WHEN "010" =>
        z_out <= a AND b;
      WHEN "011" =>
        z_out <= a OR b;
      WHEN "100" =>
        temp := add2(a,b);
        z_out <= temp(3 DOWNTO 0);
        flags(2) <= temp(4);
--        z_out <= add2(a,b)(3 DOWNTO 0);
--        flags(2) <= add2(a, b)(4);
      WHEN "101" =>
        temp := sub2(a,b);
        z_out <= temp(3 DOWNTO 0);
        flags(2) <= temp(4);
      WHEN "110" =>
        IF a > b THEN
          z_out <= a;
          flags(1) <= '1';
        ELSIF b > a THEN
          z_out <= b;
        END IF;
      WHEN "111" =>
        IF a < b THEN
          z_out <= a;
          flags(0) <= '1';
        ELSIF b < a THEN
          z_out <= b;
        END IF;
      WHEN OTHERS => NULL;
    END CASE;
  END PROCESS;
END behavioral;