-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;


ENTITY sequential_and_or IS
  PORT (a, b, c : IN std_logic; 
        z : OUT std_logic);
END;

ARCHITECTURE behavioral OF sequential_and_or IS
  SIGNAL t : std_logic;
BEGIN
  -- correct synthesis is enforced by t in the sensitivity list
  PROCESS (a, b, c, t)
  BEGIN 
    z <= '0'; t <= '0';
    t <= a AND b;
    z <= t OR c;
  END PROCESS;
END behavioral;