-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;


ENTITY fault_tolerant_adder IS
  PORT (a, b : IN std_logic_vector (7 DOWNTO 0); 
        s : INOUT std_logic_vector (7 DOWNTO 0);
        failed : OUT std_logic);
END;

ARCHITECTURE dataflow OF fault_tolerant_adder IS
  FUNCTION mod3add (a, b : IN std_logic_vector (1 DOWNTO 0)) RETURN std_logic_vector IS
    VARIABLE ai, bi, si : INTEGER;  
    VARIABLE ss : std_logic_vector (1 DOWNTO 0);
  BEGIN
    ai := evec2int (a);
    bi := evec2int (b);
    si := ai + bi;
    CASE si IS -- MOD 3
      WHEN 0 => ss := "00";
      WHEN 1 => ss := "01";
      WHEN 2 => ss := "10";
      WHEN 3 => ss := "00";
      WHEN 4 => ss := "01";
      WHEN 5 => ss := "10";
      WHEN OTHERS => ss := "00";
    END CASE;
    RETURN ss;
  END mod3add;            
  FUNCTION residue3 (a : IN std_logic_vector (7 DOWNTO 0)) RETURN std_logic_vector IS
    VARIABLE s1, s2 : std_logic_vector (1 DOWNTO 0);  
  BEGIN
    s1 := mod3add (a (1 DOWNTO 0), a (3 DOWNTO 2));     
    s2 := mod3add (a (5 DOWNTO 4), a (7 DOWNTO 6));     
    RETURN mod3add (s1, s2);
  END residue3;
  SIGNAL ra, rb, rs1, rs2 : std_logic_vector (1 DOWNTO 0);
BEGIN
  ra <= residue3 (a);
  rb <= residue3 (b);
  s <= a + b;  
  rs1 <= residue3 (s);
  rs2 <= mod3add (ra, rb);
  failed <= '0' WHEN rs1 = rs2 ELSE '1';
END dataflow;