-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY select_bus IS
  PORT (a, b, c : IN std_logic_vector (7 DOWNTO 0); 
        sa, sb, sc : IN std_logic;
        z : OUT std_logic_vector (7 DOWNTO 0));
END;

ARCHITECTURE dataflow OF select_bus IS
BEGIN
  z <= a WHEN sa = '1' ELSE "ZZZZZZZZ";
  z <= b WHEN sb = '1' ELSE "ZZZZZZZZ";
  z <= c WHEN sc = '1' ELSE "ZZZZZZZZ";
END dataflow;