-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY divider_counter IS
  PORT (clock, reset : IN std_logic; divide_out : OUT std_logic);
END;

ARCHITECTURE behavioral OF divider_counter IS
BEGIN
  dividing : PROCESS (clock)
    CONSTANT divide_by : INTEGER := 13;
    VARIABLE count : INTEGER := 0; 
  BEGIN
    IF (clock'EVENT and CLOCK = '1') THEN
      IF reset = '1' THEN 
        count := 0;
      ELSE 
        count := count - 1;
      END IF;
      IF count = 0 THEN
        divide_out <= '1';
        count := divide_by;
      ELSE
        divide_out <= '0';
      END IF;
    END IF;
  END PROCESS;
END behavioral;