-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY universal_synchronous_counter IS
  PORT (clock, reset, enable, updown : IN std_logic;
        count_out : INOUT std_logic_vector (7 DOWNTO 0));
END universal_synchronous_counter;

ARCHITECTURE behavioral OF universal_synchronous_counter IS
BEGIN
  counting : PROCESS (clock)
  BEGIN
    IF (clock = '1' AND clock'EVENT) THEN
      IF reset = '1' THEN
        count_out <= "00000000";
      ELSE
        IF enable = '1' AND updown = '1' THEN
          count_out <= count_out + "01";
        ELSIF enable = '1' AND updown = '0' THEN
          count_out <= count_out - "01";
        END IF;
      END IF;
    END IF;
  END PROCESS;
END behavioral;