-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY basic_up_counter IS
  PORT (clock : IN std_logic;
        count_out : INOUT std_logic_vector (7 DOWNTO 0) := "00000000");
END;

ARCHITECTURE behavioral OF basic_up_counter IS
BEGIN
  counting : PROCESS (clock)
  BEGIN
    IF (clock = '1' AND clock'EVENT) THEN
      count_out <= count_out + "01";
    END IF;
  END PROCESS;
END behavioral;