-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\REG1.VHD D:\EXEMPLAR\TUTORI
-- AL\HARDWARE\REG1.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP14.$$$ 
-- Version V2.1.4
-- Definition of  REG1
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 09:35:06 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity REG1 is
   port (
      D, C : in std_logic ;
      Z : out std_logic) ;
end REG1 ;

architecture exemplar of REG1 is
 
begin
   vh_3 : DLA port map ( D=>D, G=>C, Q=>Z);

end exemplar ;