-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\REG0.VHD D:\EXEMPLAR\TUTORI
-- AL\HARDWARE\REG0.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP10.$$$ 
-- Version V2.1.4
-- Definition of  REG0
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 08:53:49 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity REG0 is
   port (
      S, R : in std_logic;
      Z : inout std_logic := '0') ;
end REG0 ;

architecture exemplar of REG0 is
   signal
      vh_0: std_logic;
 
begin
   g1000 : AND2I1 port map ( Q=>vh_0, A=>Z, B=>R);
   g1001 : OR2I0 port map ( Q=>Z, A=>vh_0, B=>S);

end exemplar ;