-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\MACHINE0.VHD D:\EXEMPLAR\TU
-- TORIAL\HARDWARE\MACHINE0.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP24.$$$ 
-- Version V2.1.4
-- Definition of  MACHINE0
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 15:24:23 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity MACHINE0 is
   port (
      X, CLK : in std_logic ;
      Z : out std_logic) ;
end MACHINE0 ;

architecture exemplar of MACHINE0 is
   signal
      PRESENT_STATE_0, PRESENT_STATE_1, vh_4, NEXT_STATE_1: std_logic ;
 
begin
   g1000 : AND2I0 port map ( Q=>Z, A=>PRESENT_STATE_0, B=>PRESENT_STATE_1);
   g1001 : AND2I0 port map ( Q=>vh_4, A=>X, B=>PRESENT_STATE_1);
   g1002 : MUX2X2 port map ( Q=>NEXT_STATE_1, A=>vh_4, B=>X, S=>PRESENT_STATE_0);
   vh_6 : DFF port map ( CLK=>CLK, D=>X, Q=>PRESENT_STATE_0);
   vh_7 : DFF port map ( CLK=>CLK, D=>NEXT_STATE_1, Q=>PRESENT_STATE_1);

end exemplar ;