-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC8.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC8.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP10.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC8
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar 10 19:16:23 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC8 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0, C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0, D_7, D_6, D_5, D_4, 
      D_3, D_2, D_1, D_0, S : in std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC8 ;

architecture exemplar of LOGIC8 is
   signal
      vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, 
      vh_11, vh_12, vh_13, vh_14, vh_15, vh_17, vh_18, vh_20, vh_21, vh_23, 
      vh_24, vh_26, vh_27, vh_29, vh_30, vh_32, vh_33, vh_34, vh_35, vh_37, 
      vh_38: std_logic ;
 
begin
   g1000 : AND2I0 port map ( Q=>vh_0, A=>D_0, B=>C_0);
   g1001 : MAJ3I0 port map ( Q=>vh_1, A=>D_1, B=>vh_0, C=>C_1);
   g1002 : MAJ3I0 port map ( Q=>vh_2, A=>D_2, B=>vh_1, C=>C_2);
   g1003 : MAJ3I0 port map ( Q=>vh_3, A=>D_3, B=>vh_2, C=>C_3);
   g1004 : MAJ3I0 port map ( Q=>vh_4, A=>D_4, B=>vh_3, C=>C_4);
   g1005 : MAJ3I0 port map ( Q=>vh_5, A=>D_5, B=>vh_4, C=>C_5);
   g1006 : MAJ3I0 port map ( Q=>vh_6, A=>D_6, B=>vh_5, C=>C_6);
   g1007 : XOR3I0 port map ( Q=>vh_7, A=>D_7, B=>vh_6, C=>C_7);
   g1008 : AND2I0 port map ( Q=>vh_8, A=>B_0, B=>A_0);
   g1009 : MAJ3I0 port map ( Q=>vh_9, A=>B_1, B=>vh_8, C=>A_1);
   g1010 : MAJ3I0 port map ( Q=>vh_10, A=>B_2, B=>vh_9, C=>A_2);
   g1011 : MAJ3I0 port map ( Q=>vh_11, A=>B_3, B=>vh_10, C=>A_3);
   g1012 : MAJ3I0 port map ( Q=>vh_12, A=>B_4, B=>vh_11, C=>A_4);
   g1013 : MAJ3I0 port map ( Q=>vh_13, A=>B_5, B=>vh_12, C=>A_5);
   g1014 : MAJ3I0 port map ( Q=>vh_14, A=>B_6, B=>vh_13, C=>A_6);
   g1015 : XOR3I0 port map ( Q=>vh_15, A=>B_7, B=>vh_14, C=>A_7);
   g1016 : MUX2X0 port map ( Q=>Z_7, A=>vh_7, B=>vh_15, S=>S);
   g1017 : XOR3I0 port map ( Q=>vh_17, A=>D_6, B=>vh_5, C=>C_6);
   g1018 : XOR3I0 port map ( Q=>vh_18, A=>B_6, B=>vh_13, C=>A_6);
   g1019 : MUX2X0 port map ( Q=>Z_6, A=>vh_17, B=>vh_18, S=>S);
   g1020 : XOR3I0 port map ( Q=>vh_20, A=>D_5, B=>vh_4, C=>C_5);
   g1021 : XOR3I0 port map ( Q=>vh_21, A=>B_5, B=>vh_12, C=>A_5);
   g1022 : MUX2X0 port map ( Q=>Z_5, A=>vh_20, B=>vh_21, S=>S);
   g1023 : XOR3I0 port map ( Q=>vh_23, A=>D_4, B=>vh_3, C=>C_4);
   g1024 : XOR3I0 port map ( Q=>vh_24, A=>B_4, B=>vh_11, C=>A_4);
   g1025 : MUX2X0 port map ( Q=>Z_4, A=>vh_23, B=>vh_24, S=>S);
   g1026 : XOR3I0 port map ( Q=>vh_26, A=>D_3, B=>vh_2, C=>C_3);
   g1027 : XOR3I0 port map ( Q=>vh_27, A=>B_3, B=>vh_10, C=>A_3);
   g1028 : MUX2X0 port map ( Q=>Z_3, A=>vh_26, B=>vh_27, S=>S);
   g1029 : XOR3I0 port map ( Q=>vh_29, A=>D_2, B=>vh_1, C=>C_2);
   g1030 : XOR3I0 port map ( Q=>vh_30, A=>B_2, B=>vh_9, C=>A_2);
   g1031 : MUX2X0 port map ( Q=>Z_2, A=>vh_29, B=>vh_30, S=>S);
   g1032 : OR2I2 port map ( Q=>vh_32, A=>D_0, B=>C_0);
   g1033 : XNOR3I0 port map ( Q=>vh_33, A=>D_1, B=>vh_32, C=>C_1);
   g1034 : OR2I2 port map ( Q=>vh_34, A=>B_0, B=>A_0);
   g1035 : XNOR3I0 port map ( Q=>vh_35, A=>B_1, B=>vh_34, C=>A_1);
   g1036 : MUX2X0 port map ( Q=>Z_1, A=>vh_33, B=>vh_35, S=>S);
   g1037 : MUX2X2 port map ( Q=>vh_37, A=>D_0, B=>D_0, S=>C_0);
   g1038 : MUX2X2 port map ( Q=>vh_38, A=>B_0, B=>B_0, S=>A_0);
   g1039 : MUX2X0 port map ( Q=>Z_0, A=>vh_37, B=>vh_38, S=>S);

end exemplar ;