-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC7.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC7.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP9.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC7
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar 10 18:06:33 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC7 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0 : in std_logic ;
      N_2, N_1, N_0 : out std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : inout std_logic ;
      F : out std_logic) ;
end LOGIC7 ;

architecture exemplar of LOGIC7 is
   signal
      vh_0, vh_2, vh_4, vh_7, vh_10, vh_11, vh_12, vh_14, vh_16, vh_17, 
      vh_18, vh_21: std_logic ;
 
begin
   g1000 : AND3I3 port map ( Q=>vh_0, A=>A_0, B=>A_2, C=>A_1);
   g1001 : AND5I3 port map ( Q=>Z_6, A=>A_6, B=>vh_0, C=>A_3, D=>A_5, E=>A_4);
   g1002 : AND3I2 port map ( Q=>vh_2, A=>vh_0, B=>A_4, C=>A_3);
   g1003 : AND4I2 port map ( Q=>Z_7, A=>A_7, B=>vh_2, C=>A_5, D=>A_6);
   g1004 : AND2I2 port map ( Q=>vh_4, A=>Z_6, B=>Z_7);
   g1005 : AND3I1 port map ( Q=>Z_4, A=>vh_0, B=>A_4, C=>A_3);
   g1006 : AND4I2 port map ( Q=>Z_5, A=>A_5, B=>vh_0, C=>A_3, D=>A_4);
   g1007 : AND3I2 port map ( Q=>vh_7, A=>vh_4, B=>Z_4, C=>Z_5);
   g1008 : INV port map ( Q=>N_2, A=>vh_7);
   g1009 : AND4I3 port map ( Q=>Z_3, A=>A_3, B=>A_2, C=>A_1, D=>A_0);
   g1010 : AND2I0 port map ( Q=>vh_10, A=>Z_3, B=>vh_7);
   g1011 : AND2I1 port map ( Q=>vh_11, A=>vh_7, B=>Z_3);
   g1012 : AND4I2 port map ( Q=>vh_12, A=>vh_11, B=>A_2, C=>A_1, D=>A_0);
   g1013 : OR3I1 port map ( Q=>N_1, A=>vh_10, B=>vh_12, C=>vh_4);
   g1014 : AND2I0 port map ( Q=>vh_14, A=>Z_5, B=>vh_4);
   g1015 : AND3I2 port map ( Q=>Z_2, A=>A_2, B=>A_0, C=>A_1);
   g1016 : AND4I2 port map ( Q=>vh_16, A=>vh_11, B=>A_1, C=>A_0, D=>Z_2);
   g1017 : AND2I0 port map ( Q=>vh_17, A=>Z_3, B=>vh_7);
   g1018 : AND2I2 port map ( Q=>vh_18, A=>Z_7, B=>vh_17);
   g1019 : OR3I1 port map ( Q=>N_0, A=>vh_14, B=>vh_16, C=>vh_18);
   g1020 : AND2I1 port map ( Q=>Z_1, A=>A_1, B=>A_0);
   Z_0 <= A_0 ;
   g1021 : AND4I3 port map ( Q=>vh_21, A=>vh_11, B=>Z_1, C=>A_0, D=>Z_2);
   g1022 : INV port map ( Q=>F, A=>vh_21);

end exemplar ;