-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC5.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC5.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP24.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC5
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Sat Mar  4 05:24:46 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC5 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0, CODE_IN_2, CODE_IN_1, 
      CODE_IN_0 : in std_logic ;
      FLAGS_2, FLAGS_1, FLAGS_0 : inout std_logic ;
      Z_OUT_3, Z_OUT_2, Z_OUT_1, Z_OUT_0 : out std_logic) ;
end LOGIC5 ;

architecture exemplar of LOGIC5 is
   signal
      vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, 
      vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, 
      vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, 
      vh_31, vh_32, vh_33, vh_34, vh_35, vh_36, vh_37, vh_38, vh_39, vh_41, 
      vh_42, vh_43, vh_44, vh_45, vh_46, vh_47, vh_48, vh_49, vh_50, vh_51, 
      vh_52, vh_53, vh_54, vh_55, vh_57, vh_58, vh_59, vh_60, vh_61, vh_62, 
      vh_63, vh_65, vh_66, vh_67, vh_68, vh_69, vh_70, vh_71, vh_72, vh_73, 
      vh_74, vh_75, vh_76, vh_77, vh_78, vh_79, vh_80, vh_81, vh_82, vh_83, 
      vh_84, vh_85, vh_86, vh_87, vh_88, vh_89, vh_90, vh_91, vh_92, vh_93, 
      vh_94, vh_95, vh_96, vh_98, vh_99, vh_100, vh_101, vh_102, vh_103, 
      vh_104, vh_105, vh_106, vh_107, vh_108, vh_109, vh_110, vh_111, vh_112, 
      vh_113, vh_115, vh_116, vh_117, vh_118, vh_119, vh_120, vh_121, vh_122, 
      vh_123, vh_124, vh_125, vh_126, vh_127, vh_128, vh_129, vh_130, vh_131, 
      vh_133, vh_134, vh_135, vh_136, vh_137, vh_138, vh_139: std_logic ;
 
begin
   g1000 : AND3I3 port map ( Q=>vh_0, A=>B_2, B=>B_1, C=>B_0);
   g1001 : OR2I0 port map ( Q=>vh_1, A=>vh_0, B=>B_3);
   g1002 : MUX2X1 port map ( Q=>vh_2, A=>B_1, B=>B_1, S=>B_0);
   g1003 : AND2I0 port map ( Q=>vh_3, A=>B_0, B=>A_0);
   g1004 : AND2I2 port map ( Q=>vh_4, A=>vh_3, B=>A_1);
   g1005 : AND2I2 port map ( Q=>vh_5, A=>vh_2, B=>vh_4);
   g1006 : AND3I0 port map ( Q=>vh_6, A=>A_1, B=>B_0, C=>A_0);
   g1007 : AND2I2 port map ( Q=>vh_7, A=>vh_5, B=>vh_6);
   g1008 : AND2I2 port map ( Q=>vh_8, A=>B_1, B=>B_0);
   g1009 : MUX2X2 port map ( Q=>vh_9, A=>vh_8, B=>vh_8, S=>B_2);
   g1010 : AND2I1 port map ( Q=>vh_10, A=>vh_9, B=>A_2);
   g1011 : AND2I2 port map ( Q=>vh_11, A=>vh_7, B=>vh_10);
   g1012 : AND2I1 port map ( Q=>vh_12, A=>A_2, B=>vh_9);
   g1013 : AND2I2 port map ( Q=>vh_13, A=>vh_11, B=>vh_12);
   g1014 : INV port map ( Q=>vh_14, A=>vh_13);
   g1015 : MUX2X1 port map ( Q=>vh_15, A=>vh_0, B=>vh_0, S=>B_3);
   g1016 : MAJ3I0 port map ( Q=>vh_16, A=>A_3, B=>vh_14, C=>vh_15);
   g1017 : XNOR3I0 port map ( Q=>vh_17, A=>vh_1, B=>vh_16, C=>A_3);
   g1018 : AND3I3 port map ( Q=>vh_18, A=>CODE_IN_0, B=>CODE_IN_2, C=>CODE_IN_1);
   g1019 : AND3I2 port map ( Q=>vh_19, A=>CODE_IN_0, B=>CODE_IN_2, C=>CODE_IN_1);
   g1020 : AND2I2 port map ( Q=>vh_20, A=>vh_18, B=>vh_19);
   g1021 : AND3I1 port map ( Q=>vh_21, A=>CODE_IN_0, B=>CODE_IN_1, C=>CODE_IN_2);
   g1022 : AND3I2 port map ( Q=>vh_22, A=>CODE_IN_1, B=>CODE_IN_0, C=>CODE_IN_2);
   g1023 : AND3I2 port map ( Q=>vh_23, A=>vh_20, B=>vh_21, C=>vh_22);
   g1024 : AND3I2 port map ( Q=>vh_24, A=>CODE_IN_2, B=>CODE_IN_0, C=>CODE_IN_1);
   g1025 : AND5I2 port map ( Q=>vh_25, A=>vh_23, B=>CODE_IN_2, C=>CODE_IN_0, D=>vh_24, E=>CODE_IN_1);
   g1026 : AND2I0 port map ( Q=>vh_26, A=>vh_17, B=>vh_25);
   g1027 : AND2I1 port map ( Q=>vh_27, A=>B_1, B=>vh_4);
   g1028 : AND3I0 port map ( Q=>vh_28, A=>A_1, B=>B_0, C=>A_0);
   g1029 : AND2I2 port map ( Q=>vh_29, A=>vh_27, B=>vh_28);
   g1030 : AND2I2 port map ( Q=>vh_30, A=>A_2, B=>B_2);
   g1031 : AND2I2 port map ( Q=>vh_31, A=>vh_29, B=>vh_30);
   g1032 : AND2I0 port map ( Q=>vh_32, A=>B_2, B=>A_2);
   g1033 : AND2I2 port map ( Q=>vh_33, A=>vh_31, B=>vh_32);
   g1034 : INV port map ( Q=>vh_34, A=>vh_33);
   g1035 : MAJ3I0 port map ( Q=>vh_35, A=>A_3, B=>vh_34, C=>B_3);
   g1036 : MUX4X6 port map ( Q=>vh_36, A=>A_3, B=>A_3, C=>A_3, D=>A_3, S0=>B_3, S1=>vh_35);
   g1037 : AND4I2 port map ( Q=>vh_37, A=>vh_23, B=>CODE_IN_2, C=>CODE_IN_1, D=>CODE_IN_0);
   g1038 : AND2I1 port map ( Q=>vh_38, A=>vh_37, B=>vh_25);
   g1039 : AND2I0 port map ( Q=>vh_39, A=>vh_36, B=>vh_38);
   g1040 : OR2I0 port map ( Q=>FLAGS_2, A=>vh_26, B=>vh_39);
   g1041 : AND3I1 port map ( Q=>vh_41, A=>CODE_IN_0, B=>CODE_IN_2, C=>CODE_IN_1);
   g1042 : AND5I2 port map ( Q=>vh_42, A=>CODE_IN_2, B=>CODE_IN_1, C=>vh_23, D=>vh_24, E=>vh_41);
   g1043 : AND2I1 port map ( Q=>vh_43, A=>vh_42, B=>CODE_IN_0);
   g1044 : AND2I1 port map ( Q=>vh_44, A=>A_3, B=>B_3);
   g1045 : AND2I1 port map ( Q=>vh_45, A=>B_3, B=>A_3);
   g1046 : AND2I1 port map ( Q=>vh_46, A=>A_2, B=>B_2);
   g1047 : AND2I1 port map ( Q=>vh_47, A=>B_2, B=>A_2);
   g1048 : AND2I1 port map ( Q=>vh_48, A=>A_1, B=>B_1);
   g1049 : AND2I1 port map ( Q=>vh_49, A=>B_1, B=>A_1);
   g1050 : AND3I2 port map ( Q=>vh_50, A=>A_0, B=>vh_49, C=>B_0);
   g1051 : AND2I2 port map ( Q=>vh_51, A=>vh_48, B=>vh_50);
   g1052 : AND2I2 port map ( Q=>vh_52, A=>vh_47, B=>vh_51);
   g1053 : AND2I2 port map ( Q=>vh_53, A=>vh_46, B=>vh_52);
   g1054 : AND2I2 port map ( Q=>vh_54, A=>vh_45, B=>vh_53);
   g1055 : AND2I2 port map ( Q=>vh_55, A=>vh_44, B=>vh_54);
   g1056 : AND2I1 port map ( Q=>FLAGS_1, A=>vh_43, B=>vh_55);
   g1057 : AND3I2 port map ( Q=>vh_57, A=>B_0, B=>vh_48, C=>A_0);
   g1058 : AND2I2 port map ( Q=>vh_58, A=>vh_49, B=>vh_57);
   g1059 : AND2I2 port map ( Q=>vh_59, A=>vh_46, B=>vh_58);
   g1060 : AND2I2 port map ( Q=>vh_60, A=>vh_47, B=>vh_59);
   g1061 : AND2I2 port map ( Q=>vh_61, A=>vh_44, B=>vh_60);
   g1062 : AND2I2 port map ( Q=>vh_62, A=>vh_45, B=>vh_61);
   g1063 : AND2I1 port map ( Q=>vh_63, A=>vh_55, B=>vh_62);
   g1064 : AND3I0 port map ( Q=>FLAGS_0, A=>vh_63, B=>CODE_IN_0, C=>vh_42);
   g1065 : AND2I0 port map ( Q=>vh_65, A=>vh_43, B=>vh_63);
   g1066 : AND2I2 port map ( Q=>vh_66, A=>FLAGS_0, B=>vh_65);
   g1067 : AND3I1 port map ( Q=>vh_67, A=>vh_42, B=>CODE_IN_0, C=>vh_55);
   g1068 : AND3I2 port map ( Q=>vh_68, A=>vh_66, B=>FLAGS_1, C=>vh_67);
   g1069 : AND3I2 port map ( Q=>vh_69, A=>vh_68, B=>vh_37, C=>vh_25);
   g1070 : AND5I2 port map ( Q=>vh_70, A=>vh_20, B=>CODE_IN_1, C=>CODE_IN_0, D=>vh_22, E=>CODE_IN_2);
   g1071 : AND6I3 port map ( Q=>vh_71, A=>vh_69, B=>CODE_IN_1, C=>vh_20, D=>vh_70, E=>CODE_IN_0, F=>CODE_IN_2);
   g1072 : AND3I0 port map ( Q=>vh_72, A=>vh_71, B=>B_3, C=>A_3);
   g1073 : OR2I2 port map ( Q=>vh_73, A=>vh_66, B=>vh_67);
   g1074 : AND3I1 port map ( Q=>vh_74, A=>vh_43, B=>vh_63, C=>FLAGS_0);
   g1075 : AND4I2 port map ( Q=>vh_75, A=>vh_20, B=>CODE_IN_1, C=>CODE_IN_2, D=>CODE_IN_0);
   g1076 : AND3I2 port map ( Q=>vh_76, A=>vh_69, B=>vh_70, C=>vh_75);
   g1077 : AND5I3 port map ( Q=>vh_77, A=>vh_76, B=>CODE_IN_0, C=>CODE_IN_1, D=>vh_18, E=>CODE_IN_2);
   g1078 : AND2I0 port map ( Q=>vh_78, A=>vh_70, B=>vh_69);
   g1079 : AND4I3 port map ( Q=>vh_79, A=>vh_73, B=>vh_74, C=>vh_77, D=>vh_78);
   g1080 : AND2I1 port map ( Q=>vh_80, A=>B_3, B=>vh_79);
   g1081 : OR3I2 port map ( Q=>vh_81, A=>vh_67, B=>vh_66, C=>FLAGS_1);
   g1082 : AND2I0 port map ( Q=>vh_82, A=>vh_70, B=>vh_69);
   g1083 : AND4I3 port map ( Q=>vh_83, A=>vh_76, B=>CODE_IN_2, C=>CODE_IN_1, D=>CODE_IN_0);
   g1084 : AND4I3 port map ( Q=>vh_84, A=>vh_81, B=>FLAGS_0, C=>vh_82, D=>vh_83);
   g1085 : AND2I1 port map ( Q=>vh_85, A=>A_3, B=>vh_84);
   g1086 : INV port map ( Q=>vh_86, A=>vh_29);
   g1087 : MAJ3I0 port map ( Q=>vh_87, A=>A_2, B=>vh_86, C=>B_2);
   g1088 : MUX4X6 port map ( Q=>vh_88, A=>A_3, B=>A_3, C=>A_3, D=>A_3, S0=>B_3, S1=>vh_87);
   g1089 : AND2I0 port map ( Q=>vh_89, A=>vh_38, B=>vh_68);
   g1090 : AND2I0 port map ( Q=>vh_90, A=>vh_88, B=>vh_89);
   g1091 : OR3I0 port map ( Q=>vh_91, A=>B_2, B=>B_1, C=>B_0);
   g1092 : XNOR3I0 port map ( Q=>vh_92, A=>vh_91, B=>A_3, C=>B_3);
   g1093 : MUX2X2 port map ( Q=>vh_93, A=>vh_13, B=>vh_13, S=>vh_92);
   g1094 : AND2I0 port map ( Q=>vh_94, A=>vh_25, B=>vh_68);
   g1095 : AND2I0 port map ( Q=>vh_95, A=>vh_93, B=>vh_94);
   g1096 : AND3I3 port map ( Q=>vh_96, A=>vh_85, B=>vh_90, C=>vh_95);
   g1097 : OR3I1 port map ( Q=>Z_OUT_3, A=>vh_72, B=>vh_80, C=>vh_96);
   g1098 : AND3I3 port map ( Q=>vh_98, A=>vh_29, B=>A_2, C=>B_2);
   g1099 : MUX2X2 port map ( Q=>vh_99, A=>A_2, B=>A_2, S=>B_2);
   g1100 : AND2I0 port map ( Q=>vh_100, A=>vh_99, B=>vh_29);
   g1101 : AND2I2 port map ( Q=>vh_101, A=>vh_98, B=>vh_100);
   g1102 : AND2I1 port map ( Q=>vh_102, A=>vh_89, B=>vh_101);
   g1103 : AND2I1 port map ( Q=>vh_103, A=>vh_89, B=>vh_29);
   g1104 : AND2I2 port map ( Q=>vh_104, A=>vh_71, B=>vh_103);
   g1105 : AND2I1 port map ( Q=>vh_105, A=>B_2, B=>vh_104);
   g1106 : AND2I1 port map ( Q=>vh_106, A=>vh_84, B=>vh_105);
   g1107 : AND2I1 port map ( Q=>vh_107, A=>A_2, B=>vh_106);
   g1108 : OR2I0 port map ( Q=>vh_108, A=>B_1, B=>B_0);
   g1109 : XNOR3I0 port map ( Q=>vh_109, A=>B_2, B=>A_2, C=>vh_108);
   g1110 : MUX2X2 port map ( Q=>vh_110, A=>vh_7, B=>vh_7, S=>vh_109);
   g1111 : AND2I0 port map ( Q=>vh_111, A=>vh_110, B=>vh_94);
   g1112 : AND2I1 port map ( Q=>vh_112, A=>B_2, B=>vh_79);
   g1113 : AND2I2 port map ( Q=>vh_113, A=>vh_111, B=>vh_112);
   g1114 : OR3I1 port map ( Q=>Z_OUT_2, A=>vh_102, B=>vh_107, C=>vh_113);
   g1115 : AND3I2 port map ( Q=>vh_115, A=>vh_89, B=>B_1, C=>A_1);
   g1116 : XOR3I0 port map ( Q=>vh_116, A=>B_1, B=>A_1, C=>B_0);
   g1117 : AND2I1 port map ( Q=>vh_117, A=>vh_94, B=>vh_116);
   g1118 : AND2I2 port map ( Q=>vh_118, A=>vh_115, B=>vh_117);
   g1119 : AND2I1 port map ( Q=>vh_119, A=>vh_3, B=>vh_118);
   g1120 : AND2I0 port map ( Q=>vh_120, A=>vh_3, B=>vh_89);
   g1121 : AND2I2 port map ( Q=>vh_121, A=>vh_71, B=>vh_120);
   g1122 : AND2I1 port map ( Q=>vh_122, A=>B_1, B=>vh_121);
   g1123 : AND2I1 port map ( Q=>vh_123, A=>vh_84, B=>vh_122);
   g1124 : AND2I1 port map ( Q=>vh_124, A=>A_1, B=>vh_123);
   g1125 : MUX2X2 port map ( Q=>vh_125, A=>A_1, B=>A_1, S=>B_1);
   g1126 : AND2I0 port map ( Q=>vh_126, A=>vh_125, B=>vh_89);
   g1127 : AND2I0 port map ( Q=>vh_127, A=>vh_94, B=>vh_116);
   g1128 : AND2I2 port map ( Q=>vh_128, A=>vh_126, B=>vh_127);
   g1129 : AND2I2 port map ( Q=>vh_129, A=>vh_3, B=>vh_128);
   g1130 : AND2I1 port map ( Q=>vh_130, A=>B_1, B=>vh_79);
   g1131 : AND2I2 port map ( Q=>vh_131, A=>vh_129, B=>vh_130);
   g1132 : OR3I1 port map ( Q=>Z_OUT_1, A=>vh_119, B=>vh_124, C=>vh_131);
   g1133 : MUX2X1 port map ( Q=>vh_133, A=>B_0, B=>B_0, S=>A_0);
   g1134 : AND2I2 port map ( Q=>vh_134, A=>vh_89, B=>vh_94);
   g1135 : OR2I0 port map ( Q=>vh_135, A=>vh_133, B=>vh_134);
   g1136 : AND2I1 port map ( Q=>vh_136, A=>B_0, B=>vh_79);
   g1137 : AND2I0 port map ( Q=>vh_137, A=>vh_3, B=>vh_71);
   g1138 : AND2I1 port map ( Q=>vh_138, A=>A_0, B=>vh_84);
   g1139 : AND4I3 port map ( Q=>vh_139, A=>vh_135, B=>vh_136, C=>vh_137, D=>vh_138);
   g1140 : INV port map ( Q=>Z_OUT_0, A=>vh_139);

end exemplar ;