-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC13.VHD D:\EXEMPLAR\TUT
-- ORIAL\HARDWARE\LOGIC13.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP8.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC13
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 08:29:03 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC13 is
   port (
      A, B, C : in std_logic ;
      Z : out std_logic) ;
end LOGIC13 ;

architecture exemplar of LOGIC13 is
   signal vh_0: std_logic ;

begin
   g1000 : AND2I0 port map ( Q=>vh_0, A=>B, B=>A);
   g1001 : OR2I0 port map ( Q=>Z, A=>vh_0, B=>C);

end exemplar ;