-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\COUNT5.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\COUNT5.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP7.$$$ 
-- Version V2.1.4
-- Definition of  COUNT5
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar  3 15:38:41 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity COUNT5 is
   port (
      CLOCK, RESET : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT5 ;

architecture exemplar of COUNT5 is
   signal
      vh_9, vh_12, vh_15, vh_18, vh_21, vh_24, vh_27, vh_30: std_logic ;
 
begin
   g1000 : OR2I0 port map ( Q=>vh_9, A=>COUNT_OUT_0, B=>RESET);
   g1001 : AND2I1 port map ( Q=>vh_12, A=>COUNT_OUT_7, B=>RESET);
   g1002 : AND2I1 port map ( Q=>vh_15, A=>COUNT_OUT_6, B=>RESET);
   g1003 : AND2I1 port map ( Q=>vh_18, A=>COUNT_OUT_5, B=>RESET);
   g1004 : AND2I1 port map ( Q=>vh_21, A=>COUNT_OUT_4, B=>RESET);
   g1005 : AND2I1 port map ( Q=>vh_24, A=>COUNT_OUT_3, B=>RESET);
   g1006 : AND2I1 port map ( Q=>vh_27, A=>COUNT_OUT_2, B=>RESET);
   g1007 : AND2I1 port map ( Q=>vh_30, A=>COUNT_OUT_1, B=>RESET);
   vh_32 : DFF port map ( CLK=>CLOCK, D=>vh_9, Q=>COUNT_OUT_7);
   vh_33 : DFF port map ( CLK=>CLOCK, D=>vh_12, Q=>COUNT_OUT_6);
   vh_34 : DFF port map ( CLK=>CLOCK, D=>vh_15, Q=>COUNT_OUT_5);
   vh_35 : DFF port map ( CLK=>CLOCK, D=>vh_18, Q=>COUNT_OUT_4);
   vh_36 : DFF port map ( CLK=>CLOCK, D=>vh_21, Q=>COUNT_OUT_3);
   vh_37 : DFF port map ( CLK=>CLOCK, D=>vh_24, Q=>COUNT_OUT_2);
   vh_38 : DFF port map ( CLK=>CLOCK, D=>vh_27, Q=>COUNT_OUT_1);
   vh_39 : DFF port map ( CLK=>CLOCK, D=>vh_30, Q=>COUNT_OUT_0);

end exemplar ;