-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\COUNT3.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\COUNT3.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP11.$$$ 
-- Version V2.1.4
-- Definition of  COUNT3
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar  2 18:06:49 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity COUNT3 is
   port (
      CLOCK, RESET, ENABLE, UPDOWN : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT3 ;

architecture exemplar of COUNT3 is
   signal
      vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, 
      vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, vh_30, 
      vh_31, vh_32, vh_33, vh_36, vh_37, vh_38, vh_39, vh_40, vh_41, vh_44, 
      vh_45, vh_46, vh_47, vh_48, vh_49, vh_50, vh_51, vh_52, vh_55, vh_56, 
      vh_57, vh_58, vh_59, vh_60, vh_61, vh_64, vh_65, vh_66, vh_67, vh_68, 
      vh_69, vh_70, vh_71, vh_72, vh_75, vh_76, vh_77, vh_78, vh_81, vh_82: 
   std_logic ;
begin
   g1000 : AND3I0 port map ( Q=>vh_9, A=>COUNT_OUT_2, B=>COUNT_OUT_1, C=>COUNT_OUT_0);
   g1001 : AND3I0 port map ( Q=>vh_10, A=>COUNT_OUT_4, B=>COUNT_OUT_3, C=>vh_9);
   g1002 : AND3I1 port map ( Q=>vh_11, A=>ENABLE, B=>UPDOWN, C=>RESET);
   g1003 : INV port map ( Q=>vh_12, A=>COUNT_OUT_6);
   g1004 : AND4I1 port map ( Q=>vh_13, A=>COUNT_OUT_5, B=>vh_10, C=>vh_11, D=>vh_12);
   g1005 : AND3I3 port map ( Q=>vh_14, A=>COUNT_OUT_2, B=>COUNT_OUT_1, C=>COUNT_OUT_0);
   g1006 : AND3I2 port map ( Q=>vh_15, A=>vh_14, B=>COUNT_OUT_4, C=>COUNT_OUT_3);
   g1007 : AND3I2 port map ( Q=>vh_16, A=>ENABLE, B=>RESET, C=>UPDOWN);
   g1008 : AND4I2 port map ( Q=>vh_17, A=>vh_15, B=>vh_16, C=>COUNT_OUT_5, D=>COUNT_OUT_6);
   g1009 : AND2I2 port map ( Q=>vh_18, A=>vh_13, B=>vh_17);
   g1010 : AND3I3 port map ( Q=>vh_19, A=>RESET, B=>vh_11, C=>vh_16);
   g1011 : AND4I3 port map ( Q=>vh_20, A=>vh_14, B=>COUNT_OUT_4, C=>COUNT_OUT_3, D=>COUNT_OUT_5);
   g1012 : AND2I1 port map ( Q=>vh_21, A=>vh_16, B=>vh_20);
   g1013 : AND2I0 port map ( Q=>vh_22, A=>COUNT_OUT_5, B=>vh_10);
   g1014 : AND2I1 port map ( Q=>vh_23, A=>vh_11, B=>vh_22);
   g1015 : AND3I3 port map ( Q=>vh_24, A=>vh_19, B=>vh_21, C=>vh_23);
   g1016 : MUX2X3 port map ( Q=>vh_25, A=>vh_11, B=>vh_16, S=>COUNT_OUT_6);
   g1017 : AND2I0 port map ( Q=>vh_26, A=>vh_24, B=>vh_25);
   g1018 : MUX2X3 port map ( Q=>vh_27, A=>vh_18, B=>vh_26, S=>COUNT_OUT_7);
   g1019 : AND3I1 port map ( Q=>vh_30, A=>vh_16, B=>vh_15, C=>COUNT_OUT_5);
   g1020 : AND3I0 port map ( Q=>vh_31, A=>vh_11, B=>COUNT_OUT_5, C=>vh_10);
   g1021 : AND2I2 port map ( Q=>vh_32, A=>vh_30, B=>vh_31);
   g1022 : MUX2X3 port map ( Q=>vh_33, A=>vh_32, B=>vh_24, S=>COUNT_OUT_6);
   g1023 : AND3I1 port map ( Q=>vh_36, A=>vh_10, B=>vh_11, C=>COUNT_OUT_5);
   g1024 : AND2I1 port map ( Q=>vh_37, A=>vh_16, B=>vh_15);
   g1025 : AND2I1 port map ( Q=>vh_38, A=>vh_11, B=>vh_10);
   g1026 : AND3I3 port map ( Q=>vh_39, A=>vh_19, B=>vh_37, C=>vh_38);
   g1027 : AND2I1 port map ( Q=>vh_40, A=>COUNT_OUT_5, B=>vh_39);
   g1028 : OR3I0 port map ( Q=>vh_41, A=>vh_30, B=>vh_36, C=>vh_40);
   g1029 : AND2I0 port map ( Q=>vh_44, A=>vh_16, B=>vh_15);
   g1030 : AND2I0 port map ( Q=>vh_45, A=>COUNT_OUT_3, B=>vh_9);
   g1031 : AND3I1 port map ( Q=>vh_46, A=>vh_45, B=>vh_11, C=>COUNT_OUT_4);
   g1032 : AND2I1 port map ( Q=>vh_47, A=>vh_14, B=>COUNT_OUT_3);
   g1033 : AND2I1 port map ( Q=>vh_48, A=>vh_16, B=>vh_47);
   g1034 : AND2I1 port map ( Q=>vh_49, A=>vh_11, B=>vh_45);
   g1035 : AND3I3 port map ( Q=>vh_50, A=>vh_19, B=>vh_48, C=>vh_49);
   g1036 : AND2I1 port map ( Q=>vh_51, A=>COUNT_OUT_4, B=>vh_50);
   g1037 : OR3I0 port map ( Q=>vh_52, A=>vh_44, B=>vh_46, C=>vh_51);
   g1038 : AND5I3 port map ( Q=>vh_55, A=>vh_14, B=>ENABLE, C=>UPDOWN, D=>COUNT_OUT_3, E=>RESET);
   g1039 : AND5I2 port map ( Q=>vh_56, A=>vh_9, B=>UPDOWN, C=>ENABLE, D=>COUNT_OUT_3, E=>RESET);
   g1040 : AND4I3 port map ( Q=>vh_57, A=>ENABLE, B=>RESET, C=>UPDOWN, D=>vh_14);
   g1041 : AND4I2 port map ( Q=>vh_58, A=>UPDOWN, B=>ENABLE, C=>RESET, D=>vh_9);
   g1042 : AND3I3 port map ( Q=>vh_59, A=>vh_19, B=>vh_57, C=>vh_58);
   g1043 : AND2I1 port map ( Q=>vh_60, A=>COUNT_OUT_3, B=>vh_59);
   g1044 : OR3I0 port map ( Q=>vh_61, A=>vh_55, B=>vh_56, C=>vh_60);
   g1045 : AND4I2 port map ( Q=>vh_64, A=>vh_14, B=>ENABLE, C=>UPDOWN, D=>RESET);
   g1046 : AND2I0 port map ( Q=>vh_65, A=>COUNT_OUT_1, B=>COUNT_OUT_0);
   g1047 : AND5I2 port map ( Q=>vh_66, A=>vh_65, B=>UPDOWN, C=>ENABLE, D=>COUNT_OUT_2, E=>RESET);
   g1048 : AND2I2 port map ( Q=>vh_67, A=>COUNT_OUT_1, B=>COUNT_OUT_0);
   g1049 : AND4I3 port map ( Q=>vh_68, A=>ENABLE, B=>RESET, C=>UPDOWN, D=>vh_67);
   g1050 : AND4I2 port map ( Q=>vh_69, A=>UPDOWN, B=>ENABLE, C=>RESET, D=>vh_65);
   g1051 : AND3I3 port map ( Q=>vh_70, A=>vh_19, B=>vh_68, C=>vh_69);
   g1052 : AND2I1 port map ( Q=>vh_71, A=>COUNT_OUT_2, B=>vh_70);
   g1053 : OR3I0 port map ( Q=>vh_72, A=>vh_64, B=>vh_66, C=>vh_71);
   g1054 : AND4I3 port map ( Q=>vh_75, A=>COUNT_OUT_1, B=>vh_11, C=>vh_16, D=>RESET);
   g1055 : MUX2X2 port map ( Q=>vh_76, A=>COUNT_OUT_1, B=>COUNT_OUT_1, S=>COUNT_OUT_0);
   g1056 : MUX2X0 port map ( Q=>vh_77, A=>vh_16, B=>vh_11, S=>vh_76);
   g1057 : OR2I0 port map ( Q=>vh_78, A=>vh_75, B=>vh_77);
   g1058 : AND2I2 port map ( Q=>vh_81, A=>vh_11, B=>vh_16);
   g1059 : MUX2X1 port map ( Q=>vh_82, A=>vh_81, B=>vh_19, S=>COUNT_OUT_0);
   vh_84 : DFF port map ( CLK=>CLOCK, D=>vh_27, Q=>COUNT_OUT_7);
   vh_85 : DFF port map ( CLK=>CLOCK, D=>vh_33, Q=>COUNT_OUT_6);
   vh_86 : DFF port map ( CLK=>CLOCK, D=>vh_41, Q=>COUNT_OUT_5);
   vh_87 : DFF port map ( CLK=>CLOCK, D=>vh_52, Q=>COUNT_OUT_4);
   vh_88 : DFF port map ( CLK=>CLOCK, D=>vh_61, Q=>COUNT_OUT_3);
   vh_89 : DFF port map ( CLK=>CLOCK, D=>vh_72, Q=>COUNT_OUT_2);
   vh_90 : DFF port map ( CLK=>CLOCK, D=>vh_78, Q=>COUNT_OUT_1);
   vh_91 : DFF port map ( CLK=>CLOCK, D=>vh_82, Q=>COUNT_OUT_0);

end exemplar ;