-- -------------------------------------------------------------------- -- (c) Copyright 1990 THE VHDL CONSULTING GROUP -- -- This source file may be used and distributed without restriction -- provided that the copyright is not removed and that the code is -- not used or distributed for profit. -- -- This is not part of the recommended practice but is provided -- to users to verify that their VHDL compiler properly executes -- the logic system. -- -------------------------------------------------------------------- -- -- File name : logic_system.test.vhdl -- Title : Regression test suite for logic_system -- Library : WORK -- Author(s) : W. Billowitch ( The VHDL Consulting Group ) -- Purpose : To automatically regression test the logic system -- : -- Notes : -- -------------------------------------------------------------------- -- Modification History : -- -------------------------------------------------------------------- -- Version No:| Author:| Mod. Date:| Changes Made: -- v2.100 | wdb | 8/04/90 | Original Code -- v2.200 | wdb | 10/08/90 | Modified 'U' propagation -- v2.300 | wdb | 10/24/90 | Changed '-' to 'D', deleted attributes -- v2.400 | wdb | 11/12/90 | Fixed numerous bugs -- -------------------------------------------------------------------- LIBRARY STD, WORK; USE std.logic_system.all; ENTITY Logic_System_Test IS END logic_system_test; ARCHITECTURE logic_system_test_arch OF Logic_System_Test IS ------------------------------------------------------------------- -- Local Types ------------------------------------------------------------------- TYPE stdlogic_1D is array (std_ulogic) of std_ulogic; TYPE stdlogic_table is array(std_ulogic, std_ulogic) of std_ulogic; ------------------------------------------------------------------- -- Resolution function ------------------------------------------------------------------- CONSTANT resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H D | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', '1' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'Z' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'W' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'L' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'H' ), -- | H | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'D' ) -- | D | ); ------------------------------------------------------------------- -- Tables for Logical Operations ------------------------------------------------------------------- -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H D | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D | ); -- truth table for "or" function CONSTANT or_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H D | | -- ---------------------------------------------------- ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D | ); -- truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H D | | -- ---------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D | ); -- truth table for "not" function CONSTANT not_table: stdlogic_1D := -- ------------------------------------------------- -- | U X 0 1 Z W L H D | -- ------------------------------------------------- ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ); SIGNAL d1 : std_logic; SIGNAL d2 : std_logic_vector ( 0 to 7 ); SIGNAL driver : std_logic; SIGNAL sig_A : std_logic; SIGNAL sig_B : std_logic; SIGNAL sig_A_vector : std_logic_vector ( 0 to 7 ); SIGNAL sig_B_vector : std_logic_vector ( 7 downto 0 ); SIGNAL sig_C_vector : std_logic_vector ( 0 to 8 ); SIGNAL sig_D_vector : std_logic_vector ( 8 downto 0 ); BEGIN one_big_test : PROCESS -- see if we can declare a few constants VARIABLE c1 : std_ulogic ; VARIABLE c2 : std_ulogic_vector ( 1 to 8 ) ; VARIABLE c3 : std_logic; -- If the compiler accepts this -- assignment, then it understands section 3.1.1 par 3 -- which states "An enumeration type is said to be a CHARACTER -- TYPE if at least one of its enumeration literals is a -- character literal." VARIABLE c4 : std_logic_vector ( 8 downto 1 ) := "UX01ZWLH" ; VARIABLE c5 : X01; BEGIN -- make sure that the state system is in tact assert ( std_ulogic'low = 'U' ) report " std_ulogic'low /= 'U' " severity FAILURE; assert ( std_ulogic'high = 'D' ) report " std_ulogic'high /= 'D' " severity FAILURE; assert ( X01'low = 'X' ) report " X01'low /= 'X' " severity FAILURE; assert ( X01'high = '1' ) report " X01'high /= '1' " severity FAILURE; -- check for the correct default value assert ( c1 = 'U' ) report "incorrect default value" severity FAILURE; assert ( c2 = ('U','U','U','U','U','U','U','U')) report "incorrect default value" severity FAILURE; assert ( c3 = 'U' ) report "incorrect default value" severity FAILURE; -- this test also checks that the compiler recognizes this -- as a "character" type array == string ! assert ( c4 = "UX01ZWLH" ) report "incorrect default value" severity FAILURE; assert ( c5 = 'X' ) report "incorrect default value" severity FAILURE; -- check defaults on resolved signals assert ( d1 = 'U' ) report "incorrect default value" severity FAILURE; assert ( d2 = "UUUUUUUU" ) report "incorrect default value" severity FAILURE; WAIT; -- forever END PROCESS; driver_1 : driver <= 'U' after 0 ns, 'X' after 90 ns, '0' after 180 ns, '1' after 270 ns, 'Z' after 360 ns, 'W' after 450 ns, 'L' after 540 ns, 'H' after 630 ns, 'D' after 720 ns; driver_2 : SIG_A <= 'U' after 0 ns, 'X' after 90 ns, '0' after 180 ns, '1' after 270 ns, 'Z' after 360 ns, 'W' after 450 ns, 'L' after 540 ns, 'H' after 630 ns, 'D' after 720 ns; driver_3 : SIG_A_vector <= "UUUUUUUU" after 0 ns, "XXXXXXXX" after 90 ns, "00000000" after 180 ns, "11111111" after 270 ns, "ZZZZZZZZ" after 360 ns, "WWWWWWWW" after 450 ns, "LLLLLLLL" after 540 ns, "HHHHHHHH" after 630 ns, "DDDDDDDD" after 720 ns; driver_4 : PROCESS CONSTANT first_position : integer := std_ulogic'pos('U'); CONSTANT last_position : integer := std_ulogic'pos('D'); VARIABLE var_a_vector : std_logic_vector ( 8 to 15 ); VARIABLE var_b_vector : std_logic_vector ( 11 downto 4 ); BEGIN for j in first_position to last_position LOOP for i in first_position to last_position LOOP driver <= std_ulogic'val(i); SIG_B <= std_ulogic'val(i); SIG_B_vector <= (Others => std_ulogic'val(i)); wait for 0 ns; -- test the resolved value assert ( driver = resolution_table (std_ulogic'val(j), std_ulogic'val(i)) ) report "resolution function failed" severity FAILURE; -- test the logic operators assert ( (Sig_A and Sig_B) = and_table ( std_ulogic'val(j), std_ulogic'val(i) )) report "AND operator broken" severity FAILURE; assert ( (Sig_A or Sig_B) = or_table ( std_ulogic'val(j), std_ulogic'val(i) )) report "OR operator broken" severity FAILURE; assert ( (Sig_A xor Sig_B) = xor_table ( std_ulogic'val(j), std_ulogic'val(i) )) report "XOR operator broken" severity FAILURE; assert ( (not Sig_B) = not_table (std_ulogic'val(i))) report "NOT operator broken" severity FAILURE; var_a_vector := (others => std_ulogic'val(j)); var_b_vector := (others => std_ulogic'val(i)); -- test the logic operators on vectors assert ( (Sig_A_vector and Sig_B_vector) = (var_a_vector and var_b_vector) ) report "VECTORED AND operator broken" severity FAILURE; assert ( (Sig_A_vector or Sig_B_vector) = (var_a_vector or var_b_vector) ) report "VECTORED OR operator broken" severity FAILURE; assert ( (Sig_A_vector xor Sig_B_vector) = (var_a_vector xor var_b_vector) ) report "VECTORED XOR operator broken" severity FAILURE; assert ( (not Sig_B_vector) = (not var_b_vector) ) report "VECTORED NOT operator broken" severity FAILURE; wait for 10 ns; END LOOP; END LOOP; assert false report "TEST COMPLETED" severity NOTE; WAIT; -- forever END PROCESS driver_4; -- ADDITIONAL TESTS NEED TO BE ADDED TO PROVE BOOLEAN OPERATOR -- CLOSURE OVER THE 9-STATE TYPE AS WELL AS OVER THE X01 AND UX01 -- SUBTYPES driver_5 : PROCESS -- VARIABLE var_C_vector : std_logic_vector ( 8 to 15 ); VARIABLE var_C_vector : std_logic_vector ( 8 to 16 ); VARIABLE var_D_vector : std_logic_vector ( 11 downto 3 ); BEGIN sig_C_vector <= "UX01ZWLHD"; WAIT FOR 0 NS; var_C_vector := convert_to_X01 ( sig_C_vector ); assert ( var_C_vector = "XX01XX01X" ); var_C_vector := convert_to_UX01 ( sig_C_vector ); assert ( var_C_vector = "UX01XX01X" ); var_C_vector := convert_to_X01 ( "UX01ZWLHD" ); assert ( var_C_vector = "XX01XX01X" ); var_C_vector := convert_to_UX01 ( "UX01ZWLHD" ); assert ( var_C_vector = "UX01XX01X" ); var_D_vector := "UX01ZWLHD"; var_C_vector := convert_to_UX01 ( var_D_vector ); assert ( var_C_vector = "UX01XX01X" ); WAIT; END PROCESS driver_5; END logic_system_test_arch; CONFIGURATION logic_system_test_cfg OF logic_system_test IS FOR logic_system_test_arch END FOR; END logic_system_test_cfg;