-- --------------------------------------------------------------------
--
--   File name :  logic_system.pkg.vhdl
--   Title     :  LOGIC_SYSTEM package ( multivalue logic system )
--   Library   :  STD
--   Author(s) :  W. Billowitch ( The VHDL Consulting Group )
--   Purpose   :  This packages defines a standard for digital designers
--             :  to use in describing the interconnection data types used in
--             :  modeling common ttl, cmos, GaAs, nmos, pmos, and ecl 
--             :  digital devices. 
--             : 
--   Notes     :  The logic system defined in this package may
--             :  be insufficient for modeling switched transistors,
--             :  since that requirement is out of the scope of this
--             :  effort.
--             :
--             :  No other declarations or definitions shall be included
--             :  in this package. Any additional declarations shall be 
--             :  placed in other orthogonal packages ( ie. timing, etc )
--             :
-- --------------------------------------------------------------------
--   Modification History :
-- --------------------------------------------------------------------
--   Version No:| Author:|  Mod. Date:| Changes Made:
--     v2.000   |  wdb   |   6/19/90  | DRAFT STANDARD
--     v2.100   |  wdb   |   7/16/90  | Addition of 'U' and '-' states
--     v2.200   |  wdb   |  10/08/90  | Modified 'U' propagation
--     v2.300   |  wdb   |  10/24/90  | Changed '-' to 'D', deleted attributes
-- --------------------------------------------------------------------

Library STD; -- library location of this package
PACKAGE logic_system is

    -------------------------------------------------------------------    
    -- Logic State System  (unresolved)
    ----------------------------UUUUUUUU---------------------------------------    
    TYPE std_ulogic is ( 'U',  -- Unitialized
                         'X',  -- Forcing  0 or 1
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance   
                         'W',  -- Weak     0 or 1
                         'L',  -- Weak     0       ( for ECL open emitter )
                         'H',  -- Weak     1       ( for open Drain or Collector )
                         'D'   -- don't care
                       );
    -------------------------------------------------------------------    
    -- Unconstrained array of std_ulogic for use with the resolution function
    -------------------------------------------------------------------    
    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) of std_ulogic;
                                    
    -------------------------------------------------------------------    
    -- Resolution function
    -------------------------------------------------------------------    
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
    
    -------------------------------------------------------------------    
    -- *** Industry Standard Logic Type ***
    -------------------------------------------------------------------    
    SUBTYPE std_logic IS resolved std_ulogic;

    -------------------------------------------------------------------    
    -- Unconstrained array of std_logic for use in declaring signal arrays
    -------------------------------------------------------------------    
    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) of std_logic;

    -------------------------------------------------------------------    
    -- Three basic states + Test
    -------------------------------------------------------------------    
    SUBTYPE X01  is std_logic RANGE 'X' to '1'; -- ('X','0','1') 
    SUBTYPE UX01 is std_logic RANGE 'U' to '1'; -- ('U','X','0','1') 

    -------------------------------------------------------------------    
    -- Unconstrained array of resolved state for use in declaring registers
    -------------------------------------------------------------------
    SUBTYPE X01_vector  IS STD_LOGIC_VECTOR;
    SUBTYPE UX01_vector IS STD_LOGIC_VECTOR;

    -------------------------------------------------------------------    
    -- Overloaded Logical Operators
    -------------------------------------------------------------------    

    FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN std_ulogic;
    FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN std_ulogic;
    FUNCTION "or"   ( l : std_ulogic; r : std_ulogic ) RETURN std_ulogic;
    FUNCTION "nor"  ( l : std_ulogic; r : std_ulogic ) RETURN std_ulogic;
    FUNCTION "xor"  ( l : std_ulogic; r : std_ulogic ) RETURN std_ulogic;
    FUNCTION "not"  ( l : std_ulogic                 ) RETURN std_ulogic;
    
    -------------------------------------------------------------------    
    -- Vectorized Overloaded Logical Operators
    -------------------------------------------------------------------    
    FUNCTION "and"  ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "or"   ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "nor"  ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "xor"  ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "not"  ( l    : std_logic_vector ) RETURN std_logic_vector;

    -------------------------------------------------------------------    
    -- Conversion Functions ( strips strength from buses + signals )
    -------------------------------------------------------------------    
    FUNCTION Convert_to_X01  ( s : std_logic_vector ) RETURN  X01_vector;
    FUNCTION Convert_to_UX01 ( s : std_logic_vector ) RETURN UX01_vector;
    FUNCTION Convert_to_X01  ( s : std_ulogic       ) RETURN  X01;
    FUNCTION Convert_to_UX01 ( s : std_ulogic       ) RETURN UX01;

    -------------------------------------------------------------------    
    -- Edge Detection
    -------------------------------------------------------------------    
    FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN boolean;
    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN boolean;

END logic_system;