USE work.multiplier_types.all;
USE work.bv_arithmetic.all;
USE std.textio.all;


ENTITY shift_reg_word IS
  PORT ( clk :        in  bit;
         load :       in  bit;
         shift :      in  bit;
         clr :        in  bit;
         d :          in  word;
         d_s :        in  bit;
         q :          out word;
         q_s :        out bit );
END shift_reg_word;


ARCHITECTURE behaviour OF shift_reg_word IS

BEGIN  --  behaviour 

  shift_reg : PROCESS (clk)
    CONSTANT Tpd_clk_q_clr : Time := 4 ns;
    CONSTANT Tpd_clk_q_load : Time := 5 ns;
    CONSTANT Tpd_clk_q_shift : Time := 6 ns;
    VARIABLE reg_value : word;
    --VARIABLE L : Line;
  Begin  --  PROCESS shift_reg 
    IF (clk = '1') THEN
      IF (clr = '1') THEN
        reg_value := word'(others => '0');
        q  <= reg_value after Tpd_clk_q_clr;
        q_s <= reg_value(0) after Tpd_Clk_Q_clr;
        --write(L, string'("shift_reg: cleared"));
        --writeline(output, L);
      ELSIF (load = '1') THEN
        reg_value := d;
        q  <= reg_value after Tpd_clk_q_load;
        q_s <= reg_value(0) after Tpd_Clk_Q_Load;
        --write(L, string'("shift_reg: loaded "));
        --write_hex(L, reg_value);
        --writeline(output, L);
      ELSIF (shift = '1') THEN
        --write(L, string'("shift_reg: shifted "));
        --write_hex(L, reg_value);
        FOR i IN 1 TO word_size-1 LOOP
          reg_value(i-1) := reg_value(i);
        END LOOP;                        --  i
        --reg_value(word_size-2 downto 0) := reg_value(word_size-1 downto 1);
        reg_value(word_size-1) := d_s;
        q  <= reg_value after Tpd_clk_q_shift;
        q_s <= reg_value(0) after Tpd_Clk_Q_shift;
        --write(L, string'(" to "));
        --write_hex(L, reg_value);
        --writeline(output, L);
      END IF;
    END IF;
  END PROCESS shift_reg;

END behaviour;