ENTITY reg_1 IS
  PORT ( clk :        in  bit;
         load :       in  bit;
         d :          in  bit;
         q :          out bit );
END reg_1;


ARCHITECTURE behaviour OF reg_1 IS

BEGIN  --  behaviour 

  reg : PROCESS (clk)
    CONSTANT Tpd_clk_q : Time := 4 ns;
  BEGIN  --  PROCESS reg 
    IF (clk = '1' AND load = '1') THEN
      q  <= d after Tpd_clk_q;
    END IF;
  END PROCESS reg;

END behaviour;