USE work.multiplier_types.all;
USE work.bv_arithmetic.all;
USE std.textio.all;

ENTITY multiplier IS
  PORT ( clk :          in  bit;
         load :         in  bit;
         multiplicand : in  word;
         multiply_by :   in  word;
         ready :        out bit;
         product_low :  inout word;
         product_high : inout word );
END multiplier;


ARCHITECTURE mixed OF multiplier IS

  COMPONENT reg_1
    PORT ( clk :        in  bit;
           load :       in  bit;
           d :          in  bit;
           q :          out bit );
  END COMPONENT;

  COMPONENT shift_reg_word
    PORT ( clk :        in  bit;
           load :       in  bit;
           shift :      in  bit;
           clr :        in  bit;
           d :          in  word;
           d_s :        in  bit;
           q :          out word;
           q_s :        out bit );
  END COMPONENT;

  COMPONENT reg_word
    PORT ( clk :        in  bit;
           load :       in  bit;
           d :          in  word;
           q :          out word);
  END COMPONENT;

  COMPONENT adder
    PORT ( a :          in  word;
           b :          in  word;
           c_in :       in  bit;
           s :          out word;
           c_out :      out bit);
  END COMPONENT;

  COMPONENT and_word
    PORT ( a :  in  bit;
           b :  in  word;
           z :  out word);
  END COMPONENT;

  SIGNAL b : word;
  SIGNAL b_or_0 : word;
  SIGNAL partial_product : word;
  SIGNAL c_in : bit;
  SIGNAL c_out : bit;
  SIGNAL c_to_p : bit;
  SIGNAL p_to_a : bit;

  SIGNAL p_and_c_load : bit;
  SIGNAL shift : bit;
  SIGNAL tied_0 : bit := '0';
  
  ALIAS a_0 : bit IS product_low(0);

BEGIN  --  mixed 

  a_reg : shift_reg_word
    port map ( clk      => clk,
               load     => load,
               shift    => shift,
               clr      => tied_0,
               d        => multiplicand,
               d_s      => p_to_a,
               q        => product_low,
               q_s      => open );

  b_reg : reg_word
    port map ( clk      => clk,
               load     => load,
               d        => multiply_by,
               q        => b );
               
  p_reg : shift_reg_word
    port map ( clk      => clk,
               load     => p_and_c_load,
               shift    => shift,
               clr      => load,
               d        => partial_product,
               d_s      => c_in,
               q        => product_high,
               q_s      => p_to_a );
               
  carry_reg : reg_1
    port map (clk       => clk,
              load      => p_and_c_load,
              d         => c_out,
              q         => c_in );
              
  b_gate : and_word
    port map ( a        => a_0,
               b        => b,
               z        => b_or_0 );
               
  the_adder : adder
    port map ( a        => product_high,
               b        => b_or_0,
               c_in     => c_in,
               s        => partial_product,
               c_out    => c_out );
               
  -----------------------------------------------------------------------------
  --  Process:   controller
  --  Purpose:  sequences register loading and shifting
  --  Inputs:   clk, load
  --  Outputs:  p_and_c_load, shift, ready
  -----------------------------------------------------------------------------
  controller : PROCESS
    CONSTANT Tpd_clk_load : Time := 5 ns;
    CONSTANT Tpd_clk_shift : Time := 5 ns;
    CONSTANT Tpd_clk_ready : Time := 5 ns;
  BEGIN  --  PROCESS controller
    p_and_c_load <= '0' after Tpd_Clk_Load;
    shift <= '0' after Tpd_clk_shift;
    ready <= '1' after Tpd_clk_ready;
    WAIT on clk until clk = '1' and load = '1';
    ready <= '0' after Tpd_clk_ready;
    FOR cycle IN 1 to word_size LOOP
      p_and_c_load <= '1' after Tpd_clk_load;
      WAIT until clk = '1';
      p_and_c_load <= '0' after Tpd_clk_load;
      shift <= '1' after Tpd_clk_shift;
      WAIT until clk = '1';
      shift <= '0' after Tpd_clk_shift;
    END LOOP;                            --  cycle
    ready <= '1' after Tpd_clk_ready;
  END PROCESS controller;

END mixed;