USE work.multiplier_types.all; USE work.bv_arithmetic.all; USE std.textio.all; ENTITY mult_test IS END mult_test; ARCHITECTURE bench OF mult_test IS COMPONENT multiplier PORT ( clk : in bit; load : in bit; multiplicand : in word; multiply_by : in word; ready : out bit; product_low : inout word; product_high : inout word ); END COMPONENT; SIGNAL clk : bit; SIGNAL load : bit; SIGNAL multiplicand : word; SIGNAL multiply_by : word; SIGNAL ready : bit; SIGNAL product_low : word; SIGNAL product_high : word; BEGIN -- bench UUT : multiplier port map ( clk, load, multiplicand, multiply_by, ready, product_low, product_high); clock_gen : PROCESS CONSTANT Tc : Time := 100 ns; BEGIN -- PROCESS clock_gen FOR i IN 1 to 500 LOOP WAIT for Tc/2; clk <= '1'; WAIT for Tc - Tc/2; clk <= '0'; END LOOP; -- i wait; END PROCESS clock_gen; tester : PROCESS VARIABLE L : line; PROCEDURE drive (a, b : word) IS CONSTANT Tdelay : Time := 6 ns; BEGIN multiplicand <= a after Tdelay; multiply_by <= b after Tdelay; load <= '1' after Tdelay; WAIT until clk = '1'; load <= '0' after Tdelay; WAIT on clk until clk = '1' and ready = '1'; END drive; BEGIN -- PROCESS tester drive(X"0000_0000", X"0000_0002"); write(L, string'("tester: X""0"" x X""2"" -> ")); write_hex(L, product_high); write(L, ' '); write_hex(L, product_low); writeline(output, L); -- drive(X"0000_0002", X"0000_0002"); write(L, string'("tester: X""2"" x X""2"" -> ")); write_hex(L, product_high); write(L, ' '); write_hex(L, product_low); writeline(output, L); -- drive(x"A5A5_A5A5", x"5A5A_5A5A"); write(L, string'("tester: x""A5A5_A5A5"" x x""5A5A_5A5A"" -> ")); write_hex(L, product_high); write(L, ' '); write_hex(L, product_low); writeline(output, L); -- drive(X"FFFF_FFFF", X"FFFF_FFFF"); write(L, string'("tester: X""FFFF_FFFF"" x X""FFFF_FFFF"" -> ")); write_hex(L, product_high); write(L, ' '); write_hex(L, product_low); writeline(output, L); -- wait; END PROCESS tester; END bench;